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data sheet v 1.1 2014-05 microcontrollers 32-bit microcontroller TC1798 32-bit single-chip microcontroller
edition 2014-05 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet v 1.1 2014-05 microcontrollers 32-bit microcontroller TC1798 32-bit single-chip microcontroller
data sheet i-1 v 1.1, 2014-05 TC1798 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 system overview of the TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.1 TC1798 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 4 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 5.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 5.1.1 parameter interpretati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 5.1.2 pad driver and pad classes summary . . . . . . . . . . . . . . . . . . . . . . . 5-95 5.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 5.1.4 pin reliability in overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98 5.1.5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100 5.1.5.1 extended range operating conditions . . . . . . . . . . . . . . . . . . . . 5-102 5.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105 5.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105 5.2.2 analog to digital converters (adcx) . . . . . . . . . . . . . . . . . . . . . . . . 5-125 5.2.3 fast analog to digital converter (fadc) . . . . . . . . . . . . . . . . . . . . . 5-132 5.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136 5.2.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137 5.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-138 5.2.6.1 calculating the 1.3 v current consumpt ion . . . . . . . . . . . . . . . . 5-140 5.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142 5.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142 5.3.2 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-143 5.3.3 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145 5.3.4 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-147 5.3.5 eray phase locked loop (eray_pll) . . . . . . . . . . . . . . . . . . . . . 5-150 5.3.6 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151 5.3.7 dap interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-153 5.3.8 micro link interface (mli) timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-154 5.3.9 micro second channel (msc) interface ti ming . . . . . . . . . . . . . . . 5-157 5.3.10 ssc master/slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159 5.3.11 eray interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-161 5.3.12 ebu timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163 5.3.12.1 bfclko output clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163 5.3.12.2 ebu asynchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163 5.3.12.3 ebu burst mode access timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-170 table of contents
data sheet i-2 v 1.1, 2014-05 TC1798 5.3.12.4 ebu arbitration signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-173 5.3.12.5 ebu ddr timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-174 5.4 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-181 5.5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184 5.5.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184 5.5.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185 5.5.3 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185 6history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
TC1798 data sheet 3 v 1.1, 2014-05
TC1798 data sheet 4 v 1.1, 2014-05
TC1798 summary of features data sheet 1 v 1.1, 2014-05 1 summary of features the sak-TC1798f-512f300el / sak-TC1798f-512f300ep has the following features: ? high-performance 32-bit super-scalar tricore v1.6 cpu with 6-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? multiply-accumulate unit able to sustain 2 mac operations per cycle ? fully pipelined floating point unit (fpu) ? 300 mhz operation at full temperature range ? 32-bit peripheral control processor with si ngle cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 200 mhz operation at full temperature range ? multiple on-chip memories ? 4 mbyte program flash memory (pflash) with ecc ? 192 kbyte data flash memory (dflash) usable for eeprom emulation ? 2 x 8 kbyte key flash ? 128 kbyte data scratch-pad ram (dspr) ? 16 kbyte instruction cache (icache) ? 32 kbyte instruction scratch-pad ram (pspr) ? 16 kbyte data cache (dache) ? 128 kbyte memory (sram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? 8-channel safe dma (sdma) controller ? sophisticated interru pt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? 64-bit cross bar interconnect between cpu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (sfi bridge) ? versatile on-chip peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and overrun error detection ? four high-speed synchronous serial channels (ssc) with programmable data length and shift direction ? four ssc guardian (sscg) modules, one for each ssc ? two serial micro second bus interfaces (msc) for serial port expansion to external power devices ? two high-speed micro link interfaces (mli) for serial inter-processor communication
TC1798 summary of features data sheet 2 v 1.1, 2014-05 ? one external bus interface (ebu) supporting different memories: asynchronous memories e.g. sram, peripheral devices ; synchronous devices e.g. burst nor flash, psram; and ddr nor flash e.g. lpddr-nvm (jedec 42.2), onfi 2.0 (limited frequency at 1.8 v i/o supply) ? one multican module with 4 can nodes and 128 free assignable message objects for high efficiency data handling via fifo buffering and gateway data transfer (one can node supports ttcan functionality) ? one flexray tm module with 2 channels (e-ray). ? two general purpose timer array modules (gpta) with additional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex input/output management ? two capture / compare 6 modules ? two general purpose 12 timer units (gpt120 and gpt121) ? 64 analog input lines for adc ? 4 independent kernels (adc0, adc1, adc2, and adc3) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? 4 different fadc input channels ? channels with impedance control and overlaid with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 8 digital input lines for sent ? communication according to the sent specification j2716 feb2008 ? 238 digital general purpose i/o lines (gpio) ? digital i/o ports with 3.3 v capability ? on-chip debug support for ocds level 1 (cpu, pcp, dma, on chip buses) ? dedicated emulation device chip available (TC1798ed) ? multi-core debugging, real time tracing, and calibration ? four/five wire jtag (ieee 1149.1) or two wire dap (device access port) interface ? power management system ? clock generation unit with pll and pll_eray ? flexible crc engine (fce) ? ieee 802.3 crc32 ethernet polynomial: 0x82608edb (crc kernel 0) ? crc32c castagnoli: 0xd419cc15 (crc kernel 1) the sak-TC1798n-512f300ep has the following features: ? high-performance 32-bit super-scalar tricore v1.6 cpu with 6-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? multiply-accumulate unit able to sustain 2 mac operations per cycle ? fully pipelined floating point unit (fpu) ? 300 mhz operation at full temperature range
TC1798 summary of features data sheet 3 v 1.1, 2014-05 ? 32-bit peripheral control processor with si ngle cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 200 mhz operation at full temperature range ? multiple on-chip memories ? 4 mbyte program flash memory (pflash) with ecc ? 192 kbyte data flash memory (dflash) usable for eeprom emulation ? 2 x 8 kbyte key flash ? 128 kbyte data scratch-pad ram (dspr) ? 16 kbyte instruction cache (icache) ? 32 kbyte instruction scratch-pad ram (pspr) ? 16 kbyte data cache (dache) ? 128 kbyte memory (sram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? 8-channel safe dma (sdma) controller ? sophisticated interru pt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? 64-bit cross bar interconnect between cpu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (sfi bridge) ? versatile on-chip peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and overrun error detection ? four high-speed synchronous serial channels (ssc) with programmable data length and shift direction ? four ssc guardian (sscg) modules, one for each ssc ? two serial micro second bus interfaces (msc) for serial port expansion to external power devices ? two high-speed micro link interfaces (mli) for serial inter-processor communication ? one external bus interface (ebu) supporting different memories: asynchronous memories e.g. sram, peripheral devices ; synchronous devices e.g. burst nor flash, psram; and ddr nor flash e.g. lpddr-nvm (jedec 42.2), onfi 2.0 (limited frequency at 1.8 v i/o supply) ? one multican module with 4 can nodes and 128 free assignable message objects for high efficiency data handling via fifo buffering and gateway data transfer (one can node supports ttcan functionality) ? two general purpose timer array modules (gpta) with additional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex input/output management ? two capture / compare 6 modules
TC1798 summary of features data sheet 4 v 1.1, 2014-05 ? two general purpose 12 timer units (gpt120 and gpt121) ? 64 analog input lines for adc ? 4 independent kernels (adc0, adc1, adc2, and adc3) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? 4 different fadc input channels ? channels with impedance control and overlaid with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 8 digital input lines for sent ? communication according to the sent specification j2716 feb2008 ? 238 digital general purpose i/o lines (gpio) ? digital i/o ports with 3.3 v capability ? on-chip debug support for ocds level 1 (cpu, pcp, dma, on chip buses) ? dedicated emulation device chip available (TC1798ed) ? multi-core debugging, real time tracing, and calibration ? four/five wire jtag (ieee 1149.1) or two wire dap (device access port) interface ? power management system ? clock generation unit with pll and pll_eray ? flexible crc engine (fce) ? ieee 802.3 crc32 ethernet polynomial: 0x82608edb (crc kernel 0) ? crc32c castagnoli: 0xd419cc15 (crc kernel 1) the sak-TC1798s-512f300ep has the following features: ? high-performance 32-bit super-scalar tricore v1.6 cpu with 6-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? multiply-accumulate unit able to sustain 2 mac operations per cycle ? fully pipelined floating point unit (fpu) ? 300 mhz operation at full temperature range ? 32-bit peripheral control processor with si ngle cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 200 mhz operation at full temperature range ? multiple on-chip memories ? 4 mbyte program flash memory (pflash) with ecc ? 192 kbyte data flash memory (dflash) usable for eeprom emulation ? 2 x 8 kbyte key flash ? 128 kbyte data scratch-pad ram (dspr) ? 16 kbyte instruction cache (icache) ? 32 kbyte instruction scratch-pad ram (pspr) ? 16 kbyte data cache (dache)
TC1798 summary of features data sheet 5 v 1.1, 2014-05 ? 128 kbyte memory (sram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? 8-channel safe dma (sdma) controller ? sophisticated interru pt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? 64-bit cross bar interconnect between cpu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (sfi bridge) ? versatile on-chip peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and overrun error detection ? four high-speed synchronous serial channels (ssc) with programmable data length and shift direction ? four ssc guardian (sscg) modules, one for each ssc ? two serial micro second bus interfaces (msc) for serial port expansion to external power devices ? two high-speed micro link interfaces (mli) for serial inter-processor communication ? one external bus interface (ebu) supporting different memories: asynchronous memories e.g. sram, peripheral devices ; synchronous devices e.g. burst nor flash, psram; and ddr nor flash e.g. lpddr-nvm (jedec 42.2), onfi 2.0 (limited frequency at 1.8 v i/o supply) ? one multican module with 4 can nodes and 128 free assignable message objects for high efficiency data handling via fifo buffering and gateway data transfer (one can node supports ttcan functionality) ? one flexray tm module with 2 channels (e-ray). ? two general purpose timer array modules (gpta) with additional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex input/output management ? two capture / compare 6 modules ? two general purpose 12 timer units (gpt120 and gpt121) ? 64 analog input lines for adc ? 4 independent kernels (adc0, adc1, adc2, and adc3) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? 4 different fadc input channels ? channels with impedance control and overlaid with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 8 digital input lines for sent ? communication according to the sent specification j2716 feb2008
TC1798 summary of features data sheet 6 v 1.1, 2014-05 ? 238 digital general purpose i/o lines (gpio) ? digital i/o ports with 3.3 v capability ? on-chip debug support for ocds level 1 (cpu, pcp, dma, on chip buses) ? dedicated emulation device chip available (TC1798ed) ? multi-core debugging, real time tracing, and calibration ? four/five wire jtag (ieee 1149.1) or two wire dap (device access port) interface ? power management system ? clock generation unit with pll and pll_eray ? flexible crc engine (fce) ? ieee 802.3 crc32 ethernet polynomial: 0x82608edb (crc kernel 0) ? crc32c castagnoli: 0xd419cc15 (crc kernel 1) ? secure hardware extension (she) ? for further information please contact your infineon representative
TC1798 summary of features data sheet 7 v 1.1, 2014-05 ordering information the ordering code for infineon microcontro llers provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the TC1798 please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. this document describes the de rivatives of the device.the table 1 enumerates these derivatives and summarizes the differences. table 1 TC1798 derivative synopsis derivative ambient temperature range sak-TC1798f-512f300el t a = -40 o c to +125 o c sak-TC1798f-512f300ep t a = -40 o c to +125 o c sak-TC1798n-512f300ep t a = -40 o c to +125 o c sak-TC1798s-512f300ep t a = -40 o c to +125 o c
TC1798 system overview of the TC1798 data sheet 8 v 1.1, 2014-05 2 system overview of the TC1798 the TC1798 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: ? reduced instruction set computing (risc) processor architecture ? digital signal processing (dsp) operations and addressing modes ? on-chip memories and peripherals dsp operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world signals. the risc load/store architecture provides high computational bandwidth with low system cost. on-chip memory and peripherals are designed to support even th e most demanding high-bandwidth real-time embedded control-systems tasks. additional high-level featur es of the TC1798 include: ? efficient memory organization: instru ction and data scratch memories, caches ? serial communication interfaces ? flexible synchronous and asynchronous modes ? peripheral control processor ? standalon e data operations and interrupt servicing ? dma controller ? dma operations and interrupt servicing ? general-purpose timers ? high-performance on-chip buses ? on-chip debugging and emulation facilities ? flexible interconnections to external components ? flexible power-management the TC1798 is a high-performance microcontroller with tricore cpu, program and data memories, buses, bus arbitration, an interr upt controller, a peripheral control processor and a dma controller and several on-chip peripherals. the TC1798 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, re al-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. the TC1798 offers several versatile on-chip per ipheral units such as serial controllers, timer units, and analog-to-digital converte rs. within the TC1798, all these peripheral units are connected to the tricore cpu/system via the flexible peripheral interconnect (fpi) bus and the cross bar interconnect (sri). several i/o lines on the TC1798 ports are reserved for these peripheral units to communicate with the external world.
TC1798 system overview of the TC1798block diagram data sheet 9 v 1.1, 2014-05 2.1 block diagram figure 1 shows the block diagram of the sak-TC1798s-512f300ep . figure 1 block diagram pmi e-ray (2 channels) ebu ocds l 1 debug int erf ace / jtag tricore cpu 16 kb pram pcp2 core 32 kb cmem interrupts bridge (sfi) dmi ldram dcache pmu1 gpta 0 gpta1 2 mb pflash 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-padl data ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp cmem: code ram in pcp xbar: sri cross bar (xbar_sri) : on chip bus slave interface : on chip bus master interface dma 16 channels (memcheck) cross bar interconnect (sri) 2 mb pflash 192 kb dflash 16 kb brom keyflash pmu0 ltca2 mli 128 kb sram xbar TC1798 multican ( 4 nodes , 128 m o) sent ( 8 channels ) interrupt system stm scu ports external request unit ccu6 (2 xcc u6) fadc 3 . 3 v e x t . f a d c s u p p l y 64 (3.3v max) (5v max) 8 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y adc3 adc2 adc1 adc0 bmu asc 2 2 2 ssc 4 sscg ssc guardian 4 she gpt120 2 msc (lvds) 2 system peripheral bus (spb) sbcu fm-pll pll e-ray fce sdma 8 channels s m/s m/s m m/s m/s m/s s s s m/s s m lmu
TC1798 system overview of the TC1798block diagram data sheet 10 v 1.1, 2014-05 figure 1 shows the block diagram of the sak-TC1798f-512f300el / sak-TC1798f- 512f300ep . figure 2 block diagram figure 1 shows the block diagram of the sak-TC1798n-512f300ep . pmi e-ray (2 channels) ebu ocds l1 debug interface/ jtag tricore cpu 16 kb pram pcp2 core 32 kb cmem interrupts bridge (sfi) dmi ldram dcache pmu1 gpta 0 gpta1 2 mb pflash 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-padl data ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp cmem: code ram in pcp xbar: sri cross bar (xbar_sri) : on chip bus slave interface : on chip bus master interface dma 16 channels (memcheck) cross bar interconnect (sri) 2 mb pflash 192 kb dflash 16 kb brom keyflash pmu0 ltca2 mli 128 kb sram xbar TC1798 multican ( 4 nodes , 128 m o) sent ( 8 channels ) interrupt system stm scu ports external request unit ccu6 (2xccu6) fadc 3 . 3 v e x t . f a d c s u p p l y 64 (3.3v max) (5v max) 8 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y adc3 adc2 adc1 adc0 bmu asc 2 2 2 ssc 4 sscg ssc guardian 4 gpt120 2 msc (lvds) 2 system peripheral bus (spb) sbcu fm-pll pll e-ray fce sdma 8 channels s m/s m/s m m/s m/s m/s s s s m/s s m lmu
TC1798 system overview of the TC1798block diagram data sheet 11 v 1.1, 2014-05 figure 3 block diagram pmi ebu ocds l1 debug int erf ace / jtag tricore cpu 16 kb pram pcp2 core 32 kb cmem in t e r ru p t s bridge (sfi) dmi ldram dcache pmu1 gpta 0 gpta1 2 mb pflash 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-padl data ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp cmem: code ram in pcp xbar: sri cross bar (xbar_sri) : on chip bus slave interface : on chip bus master interface dma 16 channels (memcheck) cross bar interconnect (sri) 2 mb pflash 192 kb dflash 16 kb brom keyflash pmu0 ltca2 mli 128 kb sram xbar TC1798 multican (4 nodes , 128 mo) sent (8 channels ) interrupt system stm scu ports external request unit ccu6 (2 xccu6) fadc 3 . 3 v e x t . f a d c s u p p l y 64 (3.3v max) (5v max) 8 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y adc3 adc2 adc1 adc0 bmu asc 2 2 2 ssc 4 sscg ssc guardian 4 gpt120 2 msc (lvds) 2 system peripheral bus (spb) sbcu fm-pll pll e-ray fce sdma 8 channels s m/s m/s m m/s m/s m/s s s s m/s s m lmu
TC1798 pinning data sheet 12 v 1.1, 2014-05 3 pinning figure 4 is showing the TC1798 logic symbol. figure 4 TC1798 logic symbol tc 1798_logsym_516 alternate functions : xtal2 xtal1 oscillator v dd 14 digital circuitry power supply v ddp 17 TC1798 fadc analog power supply v ar efx v agndx v ddm adc0 /adc1 / adc2 /adc3 analog power supply an[71:0 ] adc / fadc analog inputs port 0 port 1 port 2 port 4 port 5 port 3 gpta / ccu6 / gpt12 gpta / ssc0 / ssc1 port 6 port 7 port 8 port 9 port 10 gpta / mli 0 / eru / ssc1 / ssc3 / ccu 6 / gpt12 ssc0 asc0 / asc1 / msc0 / msc1 / lvds / mli 0 / ccu6 / gpt12 eru / adc-mux / ssc3 mli1 / gpta / sent / ccu6 / gpt12 4 v d d ebu 8 v ssosc / v ss v ddosc3 2 n.c. 51 v ddosc 4 6 15 8 8 12 16 16 16 14 16 16 gpta / hwcfg / e-ray / gpt12 port 11 16 ebu port 12 8 ebu port 13 16 gpta / ebu port 14 16 gpta / ebu / ccu6 / gpt12 port 15 ebu / ccu6 / gpt12 16 port 16 13 ebu v ssm trst tck / dap0 tdi / brkin/ brkout tdo /brkout/ dap2 / brkin tms / dap1 ocds / jtag control testmode esr0 porst general control esr1 v ddpf3 v ddpf v ssmf v ssaf v fagnd v faref v ddmf v ddaf asc0 / asc1 / ssc1 / can / e-ray / ccu6 / gpt12 msc0 / msc1 / gpta / sent / ccu6 / gpt12 gpta / ssc2 / ccu6 / gpt12 port 17 16 port 18 8 sent (overlay with analog inputs ) ssc2 3 3 v ss 77 v ddsb 2 (ed only, n. c. in pd) v ddfl3 2 1) 1) 1) only available for sak -tc- 1798 s-512 f300 ep / sak -tc- 1798 f-512 f300 ep / sak -tc- 1798 f-512 f300 el
TC1798 pinningTC1798 pin configuration data sheet 13 v 1.1, 2014-05 3.1 TC1798 pin configuration this chapter shows the pin configuratio n of the TC1798 package pg-lfbga- 516. figure 5 TC1798 pinning for pg-lfbga- 516 package 30 2 9 2 8 2 7 2 6 2 5 2 4 2 3 22 21 20 1 9 1 8 1 7 1 6 15 1 4 1 3 12 11 10 9 8 7 6 5 ak vss p15.13 p16.2 p16.8 p15.1 p15.8 p15.3 p16.4 vss vdde p15.12 p15.7 p15.5 p16.0 vssp vddp p4.15 nc nc vssmf va gnd3 va gnd1 an71 an69 an67 an65 aj vdd vss p15.10 p15.9 p15.0 p15.2 p15.11 p16.5 vss vdde p16.3 p16.1 p15.6 p15.4 vssp vddp p4.13 p4.11 nc vssmf va gnd2 va ref3 an70 an68 an66 an64 ah p15.15 vdd ag p15.14 p16.6 af p14.15 p16.7 ae p14.13 p14.14 vss p14.6 p14.8 vss p10.5 p10.0 p10.3 p4.7 p4.3 vssp v ssm f an30 an26 va gnd0 va ref0 an39 p17.11 an37 p17.9 an34 an1 nc ad p14.11 p14.12 vdd vss p14.4 vdde p10.4 p10.1 p4.10 p4.6 p4.2 vddp vf agnd an29 an25 va ref2 va ref1 an38 p17.10 an36 p17.8 an33 an2 an3 ac p14.9 p14.10 p14.2 vdd an4 an44 ab p14.7 p16.12 p14.0 p13.15 vss p10.2 p4.14 p4.9 p4.5 p4.1 vdd mf vfa ref an28 an24 an43 p17.15 an41 p17.13 an47 an32 an5 an45 aa p14.5 p16.11 p13.14 p13.13 vdd vss p4.12 p4.8 p4.4 p4.0 vdd af an31 an27 an35 an42 p17.14 an40 p17.12 an7 an0 an6 an46 y p14.3 p16.10 p13.12 p13.11 p13. 1 0 vdd an8 p17.0 an9 p17.1 vddm vssm w p14.1 p16.9 p13.9 p13.8 p13.7 p13.6 vdd vss vss vss vss vdd an10 p17.2 an11 p17.3 an12 p17.4 an13 p17.5 v p12.4 p12.5 p13.5 p13.4 p13.3 p13.2 vdd vss vss vss vss vdd an16 an17 an14 p17.6 an15 p17.7 u vdde vdde vdde vdde p13.1 p13.0 vss vss vss vss vss vss an18 an19 an20 an21 t vss vss vss vss vdd pf3 vdd fl3 vss vss vss vss vss vss vss vss nc nc an22 an23 r vss osc vss osc xtal1 xtal2 vdd pf vdd osc3 vss vss vss vss vss vss vss vss vdd fl3 p7.5 vddp vssp p p12.2 p12.3 vss osc vdd osc tdi tms vss vss vss vss vss vss p7.4 p7.3 p7.2 p7.1 n p12.0 p12.1 tck trst tdo p9.14 vdd vss vss vss vss vdd p7.0 p1.1 p1.12 p1.0 m p11.14 p11.15 esr1 esr0 test mode p9.13 vdd vss vss vss vss vdd p1.9 p8.6 p1.6 p1.7 l p11.12 p11.13 p9.10 porst p9.5 p9.6 p8.5 p8.7 p8.4 p8.0 k p11.10 p11.11 p9.7 p9.8 p9.0 vssp p5.5 p3.0 p3.4 p3.12 p0.1 p0.3 p0.5 p0.7 p2.6 p8.1 vssp p8.2 p8.3 p6.15 j p11.8 p11.9 p9.2 p9.1 vssp p5.7 p5.2 p5.12 p3.10 p0.0 p0.2 p0.4 p0.6 p2.10 p2.5 p2.4 p6.7 vssp p6.11 p6.14 h p11.6 p11.7 p9.3 p9.4 p6.10 p6.13 g p11.4 p11.5 p5.6 vssp vddp p5.9 p5.8 p5.3 p5.13 p5.14 p0.10 p0.13 vddp p0.9 p2.12 p2.7 p2.3 p6.8 p6.4 vddp vssp p6.12 f p11.2 p11.3 vssp vddp p5.4 p5.11 p5.10 p5.0 p5.1 p5.15 p0.11 p0.12 vssp p0.14 p2.14 p2.8 p2.2 p6.9 p6.6 p6.5 vddp nc e p11.0 p11.1 d p12.6 p12.7 c vdde nc b vss vssp vddp p9.12 nc nc nc nc p3.1 p3.3 p3.6 p3.8 p3.11 nc vddp vssp nc p3.14 p0.8 p18.0 p18.2 p18.4 p18.6 p2.13 p2.9 nc a vssp vddp p9.9 p9.11 nc nc nc nc p3.2 p3.5 p3.7 p3.9 p3.13 nc vddp vssp nc p3.15 p0.15 p18.1 p18.3 p18.5 p18.7 p2.15 p2.11 nc 4 3 21 nc nc nc nc nc nc nc nc nc nc an62 an63 an60 an61 an58 an59 an56 an57 an54 an55 an52 an53 an50 an51 vssm vssm an48 an49 nc nc nc nc vddp vddp vssp vssp p7. 6 p7. 7 nc nc p1. 2 p1. 3 p1. 8 p1. 4 p1.10 p1.11 p1.5 p1.13 p1.14 p1.15 nc nc nc nc nc nc nc nc nc nc nc vddp vssp nc nc nc vddp nc
TC1798 pinningTC1798 pin configuration data sheet 14 v 1.1, 2014-05 table 2 pin definitions and functions (pg-lfbga- 516 package) pin symbol ctrl. type function port 0 j17 p0.0 i/o a1+/ pu port 0 general purpose i/o line 0 hwcfg0 i hardware configuration input 0 out56 o1 out56 line of gpta0 out56 o2 out56 line of gpta1 out80 o3 out80 line of ltca2 k16 p0.1 i/o a1/ pu port 0 general purpose i/o line 1 hwcfg1 i hardware configuration input 1 out57 o1 out57 line of gpta0 out57 o2 out57 line of gpta1 out81 o3 out81 line of ltca2 j16 p0.2 i/o a2/ pu port 0 general purpose i/o line 2 hwcfg2 i hardware configuration input 2 out58 o1 out58 line of gpta0 out58 o2 out58 line of gpta1 out82 o3 out82 line of ltca2 k15 p0.3 i/o a1/ pu port 0 general purpose i/o line 3 hwcfg3 i hardware configuration input 3 out59 o1 out59 line of gpta0 out59 o2 out59 line of gpta1 out83 o3 out83 line of ltca2
TC1798 pinningTC1798 pin configuration data sheet 15 v 1.1, 2014-05 j15 p0.4 i/o a1/ pu port 0 general purpose i/o line 4 hwcfg4 i hardware configuration input 4 out60 o1 out60 line of gpta0 out60 o2 out60 line of gpta1 evto0 o3 mcds output event 0 1) k14 p0.5 i/o a1/ pu port 0 general purpose i/o line 5 hwcfg5 i hardware configuration input 5 out61 o1 out61 line of gpta0 out61 o2 out61 line of gpta1 evto1 o3 mcds output event 1 1) j14 p0.6 i/o a2/ pu port 0 general purpose i/o line 6 hwcfg6 i hardware configuration input 6 out62 o1 out62 line of gpta0 out62 o2 out62 line of gpta1 evto2 o3 mcds output event 2 1) k13 p0.7 i/o a1/ pu port 0 general purpose i/o line 7 hwcfg7 i hardware configuration input 7 out63 o1 out63 line of gpta0 out63 o2 out63 line of gpta1 evto3 o3 mcds output event 3 1) b12 p0.8 i/o a1/ pu port 0 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 16 v 1.1, 2014-05 g14 p0.9 i/o a1/ pu port 0 general purpose i/o line 9 rxda0 i e-ray channel a receive data input 0 2) reserved o1 - reserved o2 - reserved o3 - g17 p0.10 i/o a2/ pu port 0 general purpose i/o line 10 txena o1 e-ray channel a transmit data output enable 2) reserved o2 - reserved o3 - f17 p0.11 i/o a2/ pu port 0 general purpose i/o line 11 t5inb i gpt120 t5ina i gpt121 txenb o1 e-ray channel b transmit data output enable 2) reserved o2 - reserved o3 - f16 p0.12 i/o a2/ pu port 0 general purpose i/o line 12 t5euda i gpt120 t5eudb i gpt121 txdb o1 e-ray channel b transmit data output 2) reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 17 v 1.1, 2014-05 g16 p0.13 i/o a1/ pu port 0 general purpose i/o line 13 rxdb0 i e-ray channel b receive data input 0 2) t5eudb i gpt120 t5euda i gpt121 reserved o1 - reserved o2 - reserved o3 - f14 p0.14 i/o a2/ pu port 0 general purpose i/o line 14 t6ina i gpt120 t6inb i gpt121 txda o1 e-ray channel a transmit data output 2) reserved o2 - reserved o3 - a12 p0.15 i/o a1/ pu port 0 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - port 1 n6 p1.0 i/o a2/ pu port 1 general purpose i/o line 0 req0 i external trigger input 0 extclk1 o1 external clock output 1 reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 18 v 1.1, 2014-05 n9 p1.1 i/o a1/ pu port 1 general purpose i/o line 1 req1 i external trigger input 1 cc60ina i ccu60 cc60inb i ccu61 cc60 o1 ccu60 reserved o2 - reserved o3 - m2 p1.2 i/o a1/ pu port 1 general purpose i/o line 2 req2 i external trigger input 2 reserved o1 - reserved o2 - reserved o3 - m1 p1.3 i/o a1/ pu port 1 general purpose i/o line 3 req3 i external trigger input 3 tready0b i mli0 transmit channel ready input b reserved o1 - reserved o2 - reserved o3 - l1 p1.4 i/o a2/ pu port 1 general purpose i/o line 4 tclk0 o1 mli0 transmit channel clock output reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 19 v 1.1, 2014-05 j2 p1.5 i/o a1/ pu port 1 general purpose i/o line 35 tready0a i mli0 transmit channel ready input a reserved o1 - reserved o2 - reserved o3 - m7 p1.6 i/o a2/ pu port 1 general purpose i/o line 6 tvalid0a o1 mli0 transmit channel valid output a slso10 o2 ssc1 slave select output line 10 cout60 o3 ccu60 m6 p1.7 i/o a2/ pu port 1 general purpose i/o line 7 cc61inb i ccu60 cc61ina i ccu61 tdata0 o1 mli0 transmit channel data output cc61 o2 ccu61 t3out o3 gpt120 l2 p1.8 i/o a1/ pu port 1 general purpose i/o line 8 rclk0a i mli0 receive channel clock input a out64 o1 out64 line of gpta0 out64 o2 out64 line of gpta1 out88 o3 out88 line of ltca2 m10 p1.9 i/o a2/ pu port 1 general purpose i/o line 9 rready0a o1 mli0 receive channel ready output a slso11 o2 ssc 1slave select output line 11 out65 o3 out65 line of gpta0 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 20 v 1.1, 2014-05 k2 p1.10 i/o a1/ pu port 1 general purpose i/o line 10 rvalid0a i mli0 receive channel valid input a out66 o1 out66 line of gpta0 out66 o2 out66 line of gpta1 out90 o3 out90 line of ltca2 k1 p1.11 i/o a1/ pu port 1 general purpose i/o line 11 rdata0a i mli0 receive channel data input a slsi3 i ssc3 input out67 o1 out67 line of gpta0 out67 o2 out67 line of gpta1 out91 o3 out91 line of ltca2 n7 p1.12 i/o a2/ pu port 1 general purpose i/o line 12 extclk0 o1 external clock output 0 out68 o2 out68 line of gpta0 out68 o3 out68 line of gpta1 j1 p1.13 i/o a1/ pu port 1 general purpose i/o line 13 rclk0b i mli0 receive channel clock input b out69 o1 out69 line of gpta0 out69 o2 out69 line of gpta1 out93 o3 out93 line of ltca2 h2 p1.14 i/o a1/ pu port 1 general purpose i/o line 14 rvalid0b i mli0 receive channel valid input b out70 o1 out70 line of gpta0 out70 o2 out70 line of gpta1 out94 o3 out94 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 21 v 1.1, 2014-05 h1 p1.15 i/o a1/ pu port 1 general purpose i/o line 15 rdata0b i mli0 receive channel data input b out71 o1 out71 line of gpta0 out71 o2 out71 line of gpta1 out95 o3 out95 line of ltca2 port 2 f11 p2.2 i/o a1+/ pu port 2 general purpose i/o line 2 slso02 o1 ssc0 slave select output line 2 slso12 o2 ssc1 slave select output line 12 slso02 and slso12 o3 ssc0 & ssc1 slave sele ct output line 2 and slave select output line 12 g11 p2.3 i/o a1+/ pu port 2 general purpose i/o line 3 slso03 o1 ssc0 slave select output line 3 slso13 o2 ssc1 slave select output line 13 slso03 and slso13 o3 ssc0 & ssc1 slave sele ct output line 3 and slave select output line 13 j11 p2.4 i/o a1+/ pu port 2 general purpose i/o line 4 slso04 o1 ssc0 slave select output line 4 slso14 o2 ssc1 slave select output line 14 slso04 and slso14 o3 ssc0 & ssc1 slave sele ct output line 4 and slave select output line 14 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 22 v 1.1, 2014-05 j12 p2.5 i/o a1+/ pu port 2 general purpose i/o line 5 slso05 o1 ssc0 slave select output line 5 slso15 o2 ssc1 slave select output line 15 slso05 and slso15 o3 ssc0 & ssc1 slave sele ct output line 5 and slave select output line 15 k12 p2.6 i/o a1+/ pu port 2 general purpose i/o line 6 slso06 o1 ssc0 slave select output line 6 slso16 o2 ssc1 slave select output line 16 slso06 and slso16 o3 ssc0 & ssc1 slave sele ct output line 6 and slave select output line 16 g12 p2.7 i/o a1+/ pu port 2 general purpose i/o line 7 slso07 o1 ssc0 slave select output line 7 slso17 o2 ssc0 slave select output line 17 slso07 and slso17 o3 ssc0 & ssc1 slave sele ct output line 7and slave select output line 17 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 23 v 1.1, 2014-05 f12 p2.8 i/o a1/ pu port 2 general purpose i/o line 8 in0 i in0 line of gpta0 in0 i in0 line of gpta1 in0 i in0 line of ltca2 ccpos0a i ccu62 t12hrb i ccu63 t3inb i gpt120 t3ina i gpt121 out0 o1 out0 line of gpta0 out0 o2 out0 line of gpta1 out0 o3 out0 line of ltca2 b6 p2.9 i/o a1/ pu port 2 general purpose i/o line 9 in1 i in1 line of gpta0 in1 i in1 line of gpta1 in1 i in1 line of ltca2 out1 o1 out1 line of gpta0 out1 o2 out1 line of gpta1 out1 o3 out1 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 24 v 1.1, 2014-05 j13 p2.10 i/o a1/ pu port 2 general purpose i/o line 10 in2 i in2 line of gpta0 in2 i in2 line of gpta1 in2 i in2 line of ltca2 t12hre i ccu60 cc61inc i ccu60 ctrapa i ccu61 cc60inc i ccu61 ctrapb i ccu63 out2 o1 out2 line of gpta0 out2 o2 out2 line of gpta1 out2 o3 out2 line of ltca2 a6 p2.11 i/o a1/ pu port 2 general purpose i/o line 11 in3 i in3 line of gpta0 in3 i in3 line of gpta1 in3 i in3 line of ltca2 out3 o1 out3 line of gpta0 out3 o2 out3 line of gpta1 out3 o3 out3 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 25 v 1.1, 2014-05 g13 p2.12 i/o a1/ pu port 2 general purpose i/o line 12 in4 i in4 line of gpta0 in4 i in4 line of gpta1 in4 i in4 line of ltca2 t12hrb i ccu62 ccpos0a i ccu63 t2inb i gpt120 t2ina i gpt121 out4 o1 out4 line of gpta0 out4 o2 out4 line of gpta1 out4 o3 out4 line of ltca2 b7 p2.13 i/o a1/ pu port 2 general purpose i/o line 13 in5 i in5 line of gpta0 in5 i in5 line of gpta1 in5 i in5 line of ltca2 out5 o1 out5 line of gpta0 out5 o2 out5 line of gpta1 out5 o3 out5 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 26 v 1.1, 2014-05 f13 p2.14 i/o a1/ pu port 2 general purpose i/o line 14 in6 i in6 line of gpta0 in6 i in6 line of gpta1 in6 i in6 line of ltca2 ccpos0a i ccu60 t12hrb i ccu61 t3ina i gpt120 t3inb i gpt121 out6 o1 out6 line of gpta0 out6 o2 out6 line of gpta1 out6 o3 out6 line of ltca2 a7 p2.15 i/o a1/ pu port 2 general purpose i/o line 15 in7 i in7 line of gpta0 in7 i in7 line of gpta1 in7 i in7 line of ltca2 out7 o1 out7 line of gpta0 out7 o2 out7 line of gpta1 out7 o3 out7 line of ltca2 port 3 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 27 v 1.1, 2014-05 k19 p3.0 i/o a1/ pu port 3 general purpose i/o line 0 in8 i in8 line of gpta0 in8 i in8 line of gpta1 in8 i in8 line of ltca2 ctrapa i ccu62 ctrpab i ccu61 cc60inc i ccu61 t12hre i ccu63 cc61inc i ccu63 t5ina i gpt120 t5inb i gpt121 out8 o1 out8 line of gpta0 out8 o2 out8 line of gpta1 out8 o3 out8 line of ltca2 b22 p3.1 i/o a1/ pu port 3 general purpose i/o line 1 in9 i in9 line of gpta0 in9 i in9 line of gpta1 in9 i in9 line of ltca2 out9 o1 out9 line of gpta0 out9 o2 out9 line of gpta1 out9 o3 out9 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 28 v 1.1, 2014-05 a22 p3.2 i/o a1/ pu port 3 general purpose i/o line 2 in10 i in10 line of gpta0 in10 i in10 line of gpta1 in10 i in10 line of ltca2 t13hre i ccu63 out10 o1 out10 line of gpta0 out10 o2 out10 line of gpta1 out10 o3 out10 line of ltca2 b21 p3.3 i/o a1/ pu port 3 general purpose i/o line 3 in11 i in11 line of gpta0 in11 i in11 line of gpta1 in11 i in11 line of ltca2 out11 o1 out11 line of gpta0 out11 o2 out11 line of gpta1 out11 o3 out11 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 29 v 1.1, 2014-05 k18 p3.4 i/o a1/ pu port 3 general purpose i/o line 4 in12 i in12 line of gpta0 in12 i in12 line of gpta1 in12 i in12 line of ltca2 t12hre i ccu62 cc61inc i ccu62 ctrapa i ccu63 ctrapb i ccu60 cc60inc i ccu63 out12 o1 out12 line of gpta0 out12 o2 out12 line of gpta1 out12 o3 out12 line of ltca2 a21 p3.5 i/o a1/ pu port 3 general purpose i/o line 5 in13 i in13 line of gpta0 in13 i in13 line of gpta1 in13 i in13 line of ltca2 out13 o1 out13 line of gpta0 out13 o2 out13 line of gpta1 out13 o3 out13 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 30 v 1.1, 2014-05 b20 p3.6 i/o a1/ pu port 3 general purpose i/o line 6 in14 i in14 line of gpta0 in14 i in14 line of gpta1 in14 i in14 line of ltca2 t13hre i ccu62 t6eudb i gpt120 t6euda i gpt121 out14 o1 out14 line of gpta0 out14 o2 out14 line of gpta1 out14 o3 out14 line of ltca2 a20 p3.7 i/o a1/ pu port 3 general purpose i/o line 7 in15 i in15 line of gpta0 in15 i in15 line of gpta1 in15 i in15 line of ltca2 out15 o1 out15 line of gpta0 out15 o2 out15 line of gpta1 out15 o3 out15 line of ltca2 b19 p3.8 i/o a1/ pu port 3 general purpose i/o line 8 in16 i in16 line of gpta0 in16 i in16 line of gpta1 in16 i in16 line of ltca2 t13hre i ccu61 out16 o1 out16 line of gpta0 out16 o2 out16 line of gpta1 out16 o3 out16 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 31 v 1.1, 2014-05 a19 p3.9 i/o a1/ pu port 3 general purpose i/o line 9 in17 i in17 line of gpta0 in17 i in17 line of gpta1 in17 i in17 line of ltca2 out17 o1 out17 line of gpta0 out17 o2 out17 line of gpta1 out17 o3 out17 line of ltca2 j18 p3.10 i/o a1+/ pu port 3 general purpose i/o line 10 in18 i in18 line of gpta0 in18 i in18 line of gpta1 in18 i in18 line of ltca2 ccpos1a i ccu62 t13hrb i ccu63 t3eudb i gpt120 t3euda i gpt121 out18 o1 out18 line of gpta0 out18 o2 out18 line of gpta1 out18 o3 out18 line of ltca2 b18 p3.11 i/o a1/ pu port 3 general purpose i/o line 11 in19 i in19 line of gpta0 in19 i in19 line of gpta1 in19 i in19 line of ltca2 out19 o1 out19 line of gpta0 out19 o2 out19 line of gpta1 out19 o3 out19 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 32 v 1.1, 2014-05 k17 p3.12 i/o a1/ pu port 3 general purpose i/o line 12 in20 i in20 line of gpta0 in20 i in20 line of gpta1 in20 i in20 line of ltca2 ccpos2a i ccu62 t12hrc i ccu63 t13hrc i ccu63 t4inb i gpt120 t4ina i gpt121 out20 o1 out20 line of gpta0 out20 o2 out20 line of gpta1 out20 o3 out20 line of ltca2 a18 p3.13 i/o a1/ pu port 3 general purpose i/o line 13 in21 i in21 line of gpta0 in21 i in21 line of gpta1 in21 i in21 line of ltca2 out21 o1 out21 line of gpta0 out21 o2 out21 line of gpta1 out21 o3 out21 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 33 v 1.1, 2014-05 b13 p3.14 i/o a1/ pu port 3 general purpose i/o line 14 in22 i in22 line of gpta0 in22 i in22 line of gpta1 in22 i in22 line of ltca2 t13hre i ccu63 out22 o1 out22 line of gpta0 out22 o2 out22 line of gpta1 out22 o3 out22 line of ltca2 a13 p3.15 i/o a1/ pu port 3 general purpose i/o line 15 in23 i in23 line of gpta0 in23 i in23 line of gpta1 in23 i in23 line of ltca2 out23 o1 out23 line of gpta0 out23 o2 out23 line of gpta1 out23 o3 out23 line of ltca2 port 4 aa17 p4.0 i/o a1+/ pu port 4 general purpose i/o line 0 in24 i in24 line of gpta0 in24 i in24 line of gpta1 in24 i in24 line of ltca2 mrst2a i ssc2 master receive input a (master mode) out24 o1 out24 line of gpta0 out24 o2 out24 line of gpta1 mrst2 o3 ssc2 slave transmit output (slave mode) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 34 v 1.1, 2014-05 ab17 p4.1 i/o a1+/ pu port 4 general purpose i/o line 1 in25 i in25 line of gpta0 in25 i in25 line of gpta1 in25 i in25 line of ltca2 mtsr2a i ssc2 slave receive input a (slave mode) mrstg2a i ssc guardian 2 master receive input a (master mode) out25 o1 out25 line of gpta0 out25 o2 out25 line of gpta1 mtsr2 o3 ssc2 master transmit output (master mode) 3) ad17 p4.2 i/o a1+/ pu port 4 general purpose i/o line 2 in26 i in26 line of gpta0 in26 i in26 line of gpta1 in26 i in26 line of ltca2 sclk2 i ssc2 input out26 o1 out26 line of gpta0 out26 o2 out26 line of gpta1 sclk2 o3 ssc2 output ae17 p4.3 i/o a1+/ pu port 4 general purpose i/o line 3 in27 i in27 line of gpta0 in27 i in27 line of gpta1 in27 i in27 line of ltca2 out27 o1 out27 line of gpta0 out27 o2 out27 line of gpta1 slso20 o3 ssc2 output table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 35 v 1.1, 2014-05 aa18 p4.4 i/o a1+/ pu port 4 general purpose i/o line 4 in28 i in28 line of gpta0 in28 i in28 line of gpta1 in28 i in28 line of ltca2 out28 o1 out28 line of gpta0 out28 o2 out28 line of gpta1 slso21 o3 ssc2 output ab18 p4.5 i/o a1+/ pu port 4 general purpose i/o line 5 in29 i in29 line of gpta0 in29 i in29 line of gpta1 in29 i in29 line of ltca2 out29 o1 out29 line of gpta0 out29 o2 out29 line of gpta1 slso22 o3 ssc2 output ad18 p4.6 i/o a1+/ pu port 4 general purpose i/o line 6 in30 i in30 line of gpta0 in30 i in30 line of gpta1 in30 i in30 line of ltca2 out30 o1 out30 line of gpta0 out30 o2 out30 line of gpta1 slso23 o3 ssc2 output table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 36 v 1.1, 2014-05 ae18 p4.7 i/o a1+/ pu port 4 general purpose i/o line 7 in31 i in31 line of gpta0 in31 i in31 line of gpta1 in31 i in31line of ltca2 t6inb i gpt120 t6ina i gpt121 out31 o1 out31 line of gpta0 out31 o2 out31 line of gpta1 slso24 o3 ssc2 output aa19 p4.8 i/o a1/ pu port 4 general purpose i/o line 8 in32 i in32 line of gpta0 in32 i in32 line of gpta1 ccpos1a i ccu60 t13hrb i ccu61 t3euda i gpt120 t3eudb i gpt121 out32 o1 out32 line of gpta0 out32 o2 out32 line of gpta1 out0 o3 out0 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 37 v 1.1, 2014-05 ab19 p4.9 i/o a1/ pu port 4 general purpose i/o line 9 in33 i in33 line of gpta0 in33 i in33 line of gpta1 ccpos2a i ccu60 t12hrc i ccu61 t13hrc i ccu61 t4ina i gpt120 t4inb i gpt121 slsi2 i ssc2 out33 o1 out33 line of gpta0 out33 o2 out33 line of gpta1 out1 o3 out1 line of ltca2 ad19 p4.10 i/o a1/ pu port 4 general purpose i/o line 10 in34 i in34 line of gpta0 in34 i in34 line of gpta1 t12hrb i ccu60 ccpos0a i ccu61 t2ina i gpt120 t2inb i gpt121 out34 o1 out34 line of gpta0 out34 o2 out34 line of gpta1 out2 o3 out2 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 38 v 1.1, 2014-05 aj13 p4.11 i/o a1/ pu port 4 general purpose i/o line 11 in35 i in35 line of gpta0 in35 i in35 line of gpta1 out35 o1 out35 line of gpta0 out35 o2 out35 line of gpta1 out3 o3 out3 line of ltca2 aa20 p4.12 i/o a1/ pu port 4 general purpose i/o line 12 in36 i in36 line of gpta0 in36 i in36 line of gpta1 t13hrb i ccu60 ccpos1a i ccu61 t2euda i gpt120 t2eudb i gpt121 out36 o1 out36 line of gpta0 out36 o2 out36 line of gpta1 out4 o3 out4 line of ltca2 aj14 p4.13 i/o a1/ pu port 4 general purpose i/o line 13 in37 i in37 line of gpta0 in37 i in37 line of gpta1 out37 o1 out37 line of gpta0 out37 o2 out37 line of gpta1 out5 o3 out5 line of ltca2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 39 v 1.1, 2014-05 ab20 p4.14 i/o a1/ pu port 4 general purpose i/o line 14 in38 i in38 line of gpta0 in38 i in38 line of gpta1 t12hrc i ccu60 t13hrc i ccu60 ccpos2a i ccu61 t4euda i gpt120 t4eudb i gpt121 out38 o1 out38 line of gpta0 out38 o2 out38 line of gpta1 out6 o3 out6 line of ltca2 ak14 p4.15 i/o a1/ pu port 4 general purpose i/o line 15 in39 i in39 line of gpta0 in39 i in39 line of gpta1 out39 o1 out39 line of gpta0 out39 o2 out39 line of gpta1 out7 o3 out7 line of ltca2 port 5 f20 p5.0 i/o a1+/ pu port 5 general purpose i/o line 0 rxd0a i asc0 receiver input/output a t6euda i gpt120 t6eudb i gpt121 rxd0a o1 asc0 receiver input/output a out72 o2 out72 line of gpta0 out72 o3 out72 line of gpta1 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 40 v 1.1, 2014-05 f19 p5.1 i/o a1+/ pu port 5 general purpose i/o line 1 txd0 o1 asc0 transmitter output a out73 o2 out73 line of gpta0 out73 o3 out73 line of gpta1 j20 p5.2 i/o a2/ pu port 5 general purpose i/o line 2 rxd1a i asc1 receiver input/output a rxd1a o1 asc1 receiver input/output a out74 o2 out74 line of gpta0 out74 o3 out74 line of gpta1 g20 p5.3 i/o a1+/ pu port 5 general purpose i/o line 3 txd1 o1 asc1 transmitter output a out75 o2 out75 line of gpta0 out75 o3 out75 line of gpta1 f23 p5.4 i/o a2/ pu port 5 general purpose i/o line 4 t13hrb i ccu62 ccpos1a i ccu63 t2eudb i gpt120 t2euda i gpt121 en00 o1 msc0 device select output 0 rready0b o2 mli0 receive channel ready output b out76 o3 out76 line of gpta0 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 41 v 1.1, 2014-05 k20 p5.5 i/o a1+/ pu port 5 general purpose i/o line 5 sdi0 i msc0 serial data input t12hrc i ccu62 t13hrc i ccu62 ccpos2a i ccu63 t4eudb i gpt120 t4euda i gpt121 out77 o1 out77 line of gpta0 out77 o2 out77 line of gpta1 out101 o3 out101 line of ltca2 g25 p5.6 i/o a2/ pu port 5 general purpose i/o line 6 cc60ina i ccu62 cc60inb i ccu63 en10 o1 msc1 device select output 0 tvalid0b o2 mli0 transmit channel valid output b cc60 o3 ccu62 j21 p5.7 i/o a1+/ pu port 5 general purpose i/o line 7 sdi1 i msc1 serial data input cc61ina i ccu62 cc61inb i ccu63 out79 o1 out79 line of gpta0 out79 o2 out79 line of gpta1 cc61 o3 ccu62 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 42 v 1.1, 2014-05 g21 p5.8 i/o f/ pu port 5 general purpose i/o line 8 cc62ina i ccu62 cc62inb i ccu63 son0 o1 msc0 differential driver serial data output negative out80 o2 out80 line of gpta0 cc62 o3 ccu62 g22 p5.9 i/o f/ pu port 5 general purpose i/o line 9 sop0a o1 msc0 differential driver serial data output positive a out81 o2 out81 line of gpta0 cout60 o3 ccu62 f21 p5.10 i/o f/ pu port 5 general purpose i/o line 10 fcln0 o1 msc0 differential driver clock output negative out82 o2 out82 line of gpta0 cout61 o3 ccu62 f22 p5.11 i/o f/ pu port 5 general purpose i/o line 11 fclp0a o1 msc0 differential driver clock output positive a out83 o2 out83 line of gpta0 cout62 o3 ccu62 j19 p5.12 i/o f/ pu port 5 general purpose i/o line 12 son1 o1 msc1 differential driver serial data output negative out84 o2 out84 line of gpta0 out84 o3 out84 line of gpta1 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 43 v 1.1, 2014-05 g19 p5.13 i/o f/ pu port 5 general purpose i/o line 13 sop1a o1 msc1 differential driver serial data output positive a out85 o2 out85 line of gpta0 out85 o3 out85 line of gpta1 g18 p5.14 i/o f/ pu port 5 general purpose i/o line 14 fcln1 o1 msc1 differential driver clock output negative out86 o2 out86 line of gpta0 out86 o3 out86 line of gpta1 f18 p5.15 i/o f/ pu port 5 general purpose i/o line 15 fclnp1a o1 msc1 differential driver clock output positive a out87 o2 out87 line of gpta0 out87 o3 out87 line of gpta1 port 6 g9 p6.4 i/o a1+/ pu port 6 general purpose i/o line 4 mtsr1 i ssc1 slave receive input (slave mode) mrstg1 i ssc guardian 1 master receive input (master mode) mtsr1 o1 ssc1 master transmit output (master mode) 3) reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 44 v 1.1, 2014-05 f8 p6.5 i/o a1+/ pu port 6 general purpose i/o line 5 mrst1 i ssc1 master receive input (master mode) mrst1 o1 ssc1 slave transmit output (slave mode) reserved o2 - reserved o3 - f9 p6.6 i/o a1+/ pu port 6 general purpose i/o line 6 sclk1 i ssc1 clock input/output sclk1 o1 ssc1 clock input/output reserved o2 - reserved o3 - j10 p6.7 i/o a1+/ pu port 6 general purpose i/o line 7 slsi1 i ssc1 slave select input t6ofl o1 gpt120 reserved o2 - reserved o3 - g10 p6.8 i/o a2/ pu port 6 general purpose i/o line 8 rxdcan0 i can node 0 receiver input 0 can node 3 receiver input 1 rxd0b i asc0 receiver input/output b capinb i gpt120 capina i gpt121 reserved o1 - rxd0b o2 asc0 receiver input/output b reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 45 v 1.1, 2014-05 f10 p6.9 i/o a2/ pu port 6 general purpose i/o line 9 txdcan0 o1 can node 0 transmitter output txd0 o2 asc0 transmitter output b t60fl o3 gpt120 h7 p6.10 i/o a2/ pu port 6 general purpose i/o line 10 rxdcan1 i can node 1 receiver input 0 can node 0 receiver input 1 rxd1b i asc1 receiver input/output b reserved o1 - rxd1b o2 asc1 receiver input/output b txena o3 e-ray channel a transmit data output enable 2) j7 p6.11 i/o a2/ pu port 6 general purpose i/o line 11 txdcan1 o1 can node 1 transmitter output txd1 o2 asc1 transmitter output b txenb o3 e-ray channel b transmit data output enable 2) g6 p6.12 i/o a1/ pu port 6 general purpose i/o line 12 rxdcan2 i can node 2 receiver input 0 can node 1 receiver input 1 rxda1 i e-ray channel a receive data input 1 2) reserved o1 - reserved o2 - cout61 o3 ccu60 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 46 v 1.1, 2014-05 h6 p6.13 i/o a2/ pu port 6 general purpose i/o line 13 txdcan2 o1 can node 2 transmitter output txda o2 e-ray channel a transmit data output 2) cout62 o3 ccu60 j6 p6.14 i/o a1/ pu port 6 general purpose i/o line 14 rxdcan3 i can node 3 receiver input 0 can node 2 receiver input 1 rxdb1 i e-ray channel b receive data input 1 2) reserved o1 - reserved o2 - cout63 o3 ccu60 k6 p6.15 i/o a2/ pu port 6 general purpose i/o line 15 cc60inb i ccu60 cc60ina i ccu61 txdcan3 o1 can node 3 transmitter output txdb o2 e-ray channel b transmit data output 2) cc60 o3 ccu61 port 7 n10 p7.0 i/o a1+/ pu port 7 general purpose i/o line 0 mrst3 i ssc3 master receive input (master mode) req4 i external trigger input 4 ad2emux2 o1 adc2 external multiple xer control output 2 mrst3 o2 ssc3 slave transmit output (slave mode) reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 47 v 1.1, 2014-05 p6 p7.1 i/o a1+/ pu port 7 general purpose i/o line 1 req5 i external trigger input 5 mtsr3 i ssc3 slave receive input (master mode) mrstg3b i ssc guardian 3 master receive input b (master mode) ad0emux2 o1 adc0 external multiple xer control output 2 mtsr3 o2 ssc3 master transmit output (master mode) 3) reserved o3 - p7 p7.2 i/o a1+/ pu port 7 general purpose i/o line 2 sclk3 i ssc3 input ad0emux0 o1 adc0 external multiple xer control output 0 sclk3 o2 ssc3 output reserved o3 - p9 p7.3 i/o a1+/ pu port 7 general purpose i/o line 3 ad0emux1 o1 adc0 external multiple xer control output 1 slso30 o2 ssc3 output reserved o3 - p10 p7.4 i/o a1+/ pu port 7 general purpose i/o line 4 req6 i external trigger input 6 ad2emux0 o1 adc2 external multiple xer control output 0 slso31 o2 ssc3 output reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 48 v 1.1, 2014-05 r9 p7.5 i/o a1+/ pu port 7 general purpose i/o line 5 req7 i external trigger input 7 ad2emux1 o1 adc2 external multiple xer control output 1 slso32 o2 ssc3 output reserved o3 - p2 p7.6 i/o a1+/ pu port 7 general purpose i/o line 6 ad1emux0 o1 adc1 external multiple xer control output 0 slso33 o2 ssc3 output reserved o3 - p1 p7.7 i/o a1+/ pu port 7 general purpose i/o line 7 ad1emux1 o1 adc1 external multiple xer control output 1 slso34 o2 ssc3 output reserved o3 - port 8 l6 p8.0 i/o a2/ pu port 8 general purpose i/o line 0 in40 i in40 line of gpta0 in40 i in40 line of gpta1 sent0 i sent digital input out40 o1 out40 line of gpta0 cout62 o2 ccu61 tclk1 o3 mli1 transmit channel clock output table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 49 v 1.1, 2014-05 k11 p8.1 i/o a1/ pu port 8 general purpose i/o line 1 in41 i in41 line of gpta0 in41 i in41 line of gpta1 tready1a i mli1 transmit channel ready input a sent1 i sent digital input cc61ina i ccu60 cc61inb i ccu61 out41 o1 out41 line of gpta0 cc61 o2 ccu60 sent1 o3 sent digital output k9 p8.2 i/o a2/ pu port 8 general purpose i/o line 2 in42 i in42 line of gpta0 in42 i in42 line of gpta1 sent2 i sent digital input capina i gpt120 capinb i gpt121 cout63 o1 ccu61 out42 o2 out42 line of gpta1 tvalid1a o3 mli1 transmit channel valid output a table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 50 v 1.1, 2014-05 k7 p8.3 i/o a2/ pu port 8 general purpose i/o line 3 in43 i in43 line of gpta0 in43 i in43 line of gpta1 sent3 i sent digital input cc62ina i ccu60 cc62inb i ccu61 out43 o1 out43 line of gpta0 cc62 o2 ccu60 tdata1 o3 mli1 transmit channel data output a l7 p8.4 i/o a1/ pu port 8 general purpose i/o line 4 in44 i in44 line of gpta0 in44 i in44 line of gpta1 rclk1a i mli1 receive channel clock input a sent4 i sent digital input cc62inb i ccu60 cc62ina i ccu61 out44 o1 out44 line of gpta0 cc62 o2 ccu61 t3out o3 gpt121 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 51 v 1.1, 2014-05 l10 p8.5 i/o a2/ pu port 8 general purpose i/o line 5 in45 i in45 line of gpta0 in45 i in45 line of gpta1 sent5 i sent digital input ctrapa i ccu60 ctrapb i ccu62 cc60inc i ccu60 t12hre i ccu61 cc61inc i ccu61 out45 o1 out45 line of gpta0 out45 o2 out45 line of gpta1 rready1a o3 mli1 receive channel ready output a m9 p8.6 i/o a1/ pu port 8 general purpose i/o line 6 in46 i in46 line of gpta0 in46 i in46 line of gpta1 rvalid1a i mli1 receive channel valid input a sent6 i sent digital input out46 o1 out46 line of gpta0 cout60 o2 ccu61 t6out o3 gpt120 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 52 v 1.1, 2014-05 l9 p8.7 i/o a1/ pu port 8 general purpose i/o line 7 in47 i in47 line of gpta0 in47 i in47 line of gpta1 rdata1a i mli1 receive channel data input a sent7 i sent digital input out47 o1 out47 line of gpta0 cout61 o2 ccu61 t6out o3 gpt121 port 9 k22 p9.0 i/o a2/ pu port 9 general purpose i/o line 0 in48 i in48 line of gpta0 in48 i in48 line of gpta1 cout63 o1 ccu62 out48 o2 out48 line of gpta1 en12 o3 msc1 device select output 2 j24 p9.1 i/o a2/ pu port 9 general purpose i/o line 1 in49 i in49 line of gpta0 in49 i in49 line of gpta1 cc60inb i ccu62 cc60ina i ccu63 cc60 o1 ccu63 out49 o2 out49 line of gpta1 en11 o3 msc1 device select output 1 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 53 v 1.1, 2014-05 j25 p9.2 i/o a2/ pu port 9 general purpose i/o line 2 in50 i in50 line of gpta0 in50 i in50 line of gpta1 cc61inb i ccu62 cc61ina i ccu63 cc61 o1 ccu63 out50 o2 out50 line of gpta1 sop1b o3 msc1 serial data output h25 p9.3 i/o a2/ pu port 9 general purpose i/o line 3 in51 i in51 line of gpta0 in51 i in51 line of gpta1 cc62inb i ccu62 cc62ina i ccu63 cc62 o1 ccu63 out51 o2 out51 line of gpta1 fclp1b o3 msc1 clock output h24 p9.4 i/o a2/ pu port 9 general purpose i/o line 4 in52 i in52 line of gpta0 in52 i in52 line of gpta1 cout60 o1 ccu63 out52 o2 out52 line of gpta1 en03 o3 msc0 device select output 3 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 54 v 1.1, 2014-05 l22 p9.5 i/o a2/ pu port 9 general purpose i/o line 5 in53 i in53 line of gpta0 in53 i in53 line of gpta1 sent1 i sent digital input cout61 o1 ccu63 out53 o2 out53 line of gpta1 en02 o3 msc0 device select output 2 l21 p9.6 i/o a2/ pu port 9 general purpose i/o line 6 in54 i in54 line of gpta0 in54 i in54 line of gpta1 sent3 i sent digital input out54 o1 out54 line of gpta0 sent3 o2 sent digital output en01 o3 msc0 device select output 1 k25 p9.7 i/o a2/ pu port 9 general purpose i/o line 7 in55 i in55 line of gpta0 in55 i in55 line of gpta1 sent4 i sent digital input out55 o1 out55 line of gpta0 sent4 o2 sent digital output sop0b o3 msc0 serial data output k24 p9.8 i/o a2/ pu port 9 general purpose i/o line 8 sent6 i sent digital input cout62 o1 ccu63 sent6 o2 sent digital output fclp0b o3 msc0 clock output table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 55 v 1.1, 2014-05 a28 p9.9 i/o a1/ pu port 9 general purpose i/o line 9 sent0 i sent digital input reserved o1 - sent0 o2 sent digital output reserved o3 - l25 p9.10 i/o a1/ pu port 9 general purpose i/o line 10 emgstop i emergency stop sent7 i sent digital input cout63 o1 ccu63 sent7 o2 sent digital output reserved o3 - a27 p9.11 i/o a1/ pu port 9 general purpose i/o line 11 sent2 i sent digital input reserved o1 - sent2 o2 sent digital output reserved o3 - b27 p9.12 i/o a1/ pu port 9 general purpose i/o line 12 sent5 i sent digital input reserved o1 - sent5 o2 sent digital output reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 56 v 1.1, 2014-05 m21 p9.13 i/o a2/ pu port 9 general purpose i/o line 13 brkin i ocds break input ectt1 i ttcan input reserved o1 - reserved o2 - reserved o3 - brkout o ocds break output n21 p9.14 i/o a2/ pu port 9 general purpose i/o line 14 brkin i ocds break input ectt2 i ttcan input req15 i external trigger input 15 reserved o1 - reserved o2 - reserved o3 - brkout o ocds break output port 10 ae20 p10.0 i/o a2/ pu port 10 general purpose i/o line 0 mrst0 i ssc0 master receive input (master mode) mrst0 o1 ssc0 slave transmit output (slave mode) reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 57 v 1.1, 2014-05 ad20 p10.1 i/o a2/ pu port 10 general purpose i/o line 1 mtsr0 i ssc0 slave receive input (slave mode) mrstg0 i ssc guardian 0 master receive input (master mode) mtsr0 o1 ssc0 master transmit output (master mode) 3) reserved o2 - reserved o3 - ab21 p10.2 i/o a1/ pu port 10 general purpose i/o line 2 slsi0 i ssc0 slave select input reserved o1 - reserved o2 - reserved o3 - ae19 p10.3 i/o a2/ pu port 10 general purpose i/o line 3 sclk0 i ssc0 clock input/output sclk0 o1 ssc0 clock input/output reserved o2 - reserved o3 - ad21 p10.4 i/o a1+/ pu port 10 general purpose i/o line 4 slso0 o1 ssc0 slave select output line 0 reserved o2 - reserved o3 - ae21 p10.5 i/o a1+/ pu port 10 general purpose i/o line 5 slso1 o1 ssc0 slave select output line 1 reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 58 v 1.1, 2014-05 port 11 e30 p11.0 i/o b/ pu port 11 general purpose i/o line 0 reserved o1 - reserved o2 - reserved o3 - a0 o ebu address bus line 0 e29 p11.1 i/o b/ pu port 11 general purpose i/o line 1 reserved o1 - reserved o2 - reserved o3 - a1 o ebu address bus line 1 f30 p11.2 i/o b/ pu port 11 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - a2 o ebu address bus line 2 f29 p11.3 i/o b/ pu port 11 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - a3 o ebu address bus line 3 g30 p11.4 i/o b/ pu port 11 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - a4 o ebu address bus line 4 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 59 v 1.1, 2014-05 g29 p11.5 i/o b/ pu port 11 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - a5 o ebu address bus line 5 h30 p11.6 i/o b/ pu port 11 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - a6 o ebu address bus line 6 h29 p11.7 i/o b/ pu port 11 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - a7 o ebu address bus line 7 j30 p11.8 i/o b/ pu port 11 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - a8 o ebu address bus line 8 j29 p11.9 i/o b/ pu port 11 general purpose i/o line 9 reserved o1 - reserved o2 - reserved o3 - a9 o ebu address bus line 9 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 60 v 1.1, 2014-05 k30 p11.10 i/o b/ pu port 11 general purpose i/o line 10 reserved o1 - reserved o2 - reserved o3 - a10 o ebu address bus line 10 k29 p11.11 i/o b/ pu port 11 general purpose i/o line 11 reserved o1 - reserved o2 - reserved o3 - a11 o ebu address bus line 11 l30 p11.12 i/o b/ pu port 11 general purpose i/o line 12 reserved o1 - reserved o2 - reserved o3 - a12 o ebu address bus line 12 l29 p11.13 i/o b/ pu port 11 general purpose i/o line 13 reserved o1 - reserved o2 - reserved o3 - a13 o ebu address bus line 13 m30 p11.14 i/o b/ pu port 11 general purpose i/o line 14 reserved o1 - reserved o2 - reserved o3 - a14 o ebu address bus line 14 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 61 v 1.1, 2014-05 m29 p11.15 i/o b/ pu port 11 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - a15 o ebu address bus line 15 port 12 n30 p12.0 i/o b/ pu port 12 general purpose i/o line 0 reserved o1 - reserved o2 - reserved o3 - a16 o ebu address bus line 16 n29 p12.1 i/o b/ pu port 12 general purpose i/o line 1 reserved o1 - reserved o2 - reserved o3 - a17 o ebu address bus line 17 p30 p12.2 i/o b/ pu port 12 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - a18 o ebu address bus line 18 p29 p12.3 i/o b/ pu port 12 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - a19 o ebu address bus line 19 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 62 v 1.1, 2014-05 v30 p12.4 i/o b/ pu port 12 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - a20 o ebu address bus line 20 v29 p12.5 i/o b/ pu port 12 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - a21 o ebu address bus line 21 d30 p12.6 i/o b/ pu port 12 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - a22 o ebu address bus line 22 d29 p12.7 i/o b/ pu port 12 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - a23 o ebu address bus line 23 port 13 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 63 v 1.1, 2014-05 u21 p13.0 i/o b/ pu port 13 general purpose i/o line 0 ad0 i ebu address/data bus line 0 out88 o1 out88 line of gpta0 out88 o2 out88 line of gpta1 out80 o3 out80 line of ltca2 ad0 o ebu address/data bus line 0 u22 p13.1 i/o b/ pu port 13 general purpose i/o line 1 ad1 i ebu address/data bus line 1 out89 o1 out89 line of gpta0 out89 o2 out89 line of gpta1 out81 o3 out81 line of ltca2 ad1 o ebu address/data bus line 1 v21 p13.2 i/o b/ pu port 13 general purpose i/o line 2 ad2 i ebu address/data bus line 2 out90 o1 out90 line of gpta0 out90 o2 out90 line of gpta1 out82 o3 out82 line of ltca2 ad2 o ebu address/data bus line 2 v22 p13.3 i/o b/ pu port 13 general purpose i/o line 3 ad3 i ebu address/data bus line 3 out91 o1 out91 line of gpta0 out91 o2 out91 line of gpta1 out83 o3 out83 line of ltca2 ad3 o ebu address/data bus line 3 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 64 v 1.1, 2014-05 v24 p13.4 i/o b/ pu port 13 general purpose i/o line 4 ad4 i ebu address/data bus line 4 out92 o1 out92 line of gpta0 out92 o2 out92 line of gpta1 out84 o3 out84 line of ltca2 ad4 o ebu address/data bus line 4 v25 p13.5 i/o b/ pu port 13 general purpose i/o line 5 ad5 i ebu address/data bus line 5 out93 o1 out93 line of gpta0 out93 o2 out93 line of gpta1 out85 o3 out85 line of ltca2 ad5 o ebu address/data bus line 5 w21 p13.6 i/o b/ pu port 13 general purpose i/o line 6 ad6 i ebu address/data bus line 6 out94 o1 out94 line of gpta0 out94 o2 out94 line of gpta1 out86 o3 out86 line of ltca2 ad6 o ebu address/data bus line 6 w22 p13.7 i/o b/ pu port 13 general purpose i/o line 7 ad7 i ebu address/data bus line 7 out95 o1 out95 line of gpta0 out95 o2 out95 line of gpta1 out87 o3 out87 line of ltca2 ad7 o ebu address/data bus line 7 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 65 v 1.1, 2014-05 w24 p13.8 i/o b/ pu port 13 general purpose i/o line 8 ad8 i ebu address/data bus line 8 out96 o1 out96 line of gpta0 out96 o2 out96 line of gpta1 out88 o3 out88 line of ltca2 ad8 o ebu address/data bus line 8 w25 p13.9 i/o b/ pu port 13 general purpose i/o line 9 ad9 i ebu address/data bus line 9 out97 o1 out97 line of gpta0 out97 o2 out97 line of gpta1 out89 o3 out89 line of ltca2 ad9 o ebu address/data bus line 9 y22 p13.10 i/o b/ pu port 13 general purpose i/o line 10 ad10 i ebu address/data bus line 10 out98 o1 out98 line of gpta0 out98 o2 out98 line of gpta1 out90 o3 out90 line of ltca2 ad10 o ebu address/data bus line 10 y24 p13.11 i/o b/ pu port 13 general purpose i/o line 11 ad11 i ebu address/data bus line 11 out99 o1 out99 line of gpta0 out99 o2 out99 line of gpta1 out91 o3 out91 line of ltca2 ad11 o ebu address/data bus line 11 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 66 v 1.1, 2014-05 y25 p13.12 i/o b/ pu port 13 general purpose i/o line 12 ad12 i ebu address/data bus line 12 out100 o1 out100 line of gpta0 out100 o2 out100 line of gpta1 out92 o3 out92 line of ltca2 ad12 o ebu address/data bus line 12 aa24 p13.13 i/o b/ pu port 13 general purpose i/o line 13 ad13 i ebu address/data bus line 13 out101 o1 out101 line of gpta0 out101 o2 out101 line of gpta1 out93 o3 out93 line of ltca2 ad13 o ebu address/data bus line 13 aa25 p13.14 i/o b/ pu port 13 general purpose i/o line 14 ad14 i ebu address/data bus line 14 out102 o1 out102 line of gpta0 out102 o2 out102 line of gpta1 out94 o3 out94 line of ltca2 ad14 o ebu address/data bus line 14 ab24 p13.15 i/o b/ pu port 13 general purpose i/o line 15 ad15 i ebu address/data bus line 15 out103 o1 out103 line of gpta0 out103 o2 out103 line of gpta1 out95 o3 out95 line of ltca2 ad15 o ebu address/data bus line 15 port 14 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 67 v 1.1, 2014-05 ab25 p14.0 i/o b/ pu port 14 general purpose i/o line 0 ad16 i ebu address/data bus line 16 cc60 o1 ccu60 out96 o2 out96 line of gpta1 out96 o3 out96 line of ltca2 ad16 o ebu address/data bus line 16 w30 p14.1 i/o b/ pu port 14 general purpose i/o line 1 ad17 i ebu address/data bus line 17 cc61 o1 ccu60 out97 o2 out97 line of gpta1 out97 o3 out97 line of ltca2 ad17 o ebu address/data bus line 17 ac25 p14.2 i/o b/ pu port 14 general purpose i/o line 2 ad18 i ebu address/data bus line 18 cc62 o1 ccu60 out98 o2 out98 line of gpta1 out98 o3 out98 line of ltca2 ad18 o ebu address/data bus line 18 y30 p14.3 i/o b/ pu port 14 general purpose i/o line 3 ad19 i ebu address/data bus line 19 cout60 o1 ccu60 out99 o2 out99 line of gpta1 out99 o3 out99 line of ltca2 ad19 o ebu address/data bus line 19 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 68 v 1.1, 2014-05 ad23 p14.4 i/o b/ pu port 14 general purpose i/o line 4 ad20 i ebu address/data bus line 20 cout61 o1 ccu60 out100 o2 out100 line of gpta1 out100 o3 out100 line of ltca2 ad20 o ebu address/data bus line 20 aa30 p14.5 i/o b/ pu port 14 general purpose i/o line 5 ad21 i ebu address/data bus line 21 cout62 o1 ccu60 out101 o2 out101 line of gpta1 out101 o3 out101 line of ltca2 ad21 o ebu address/data bus line 21 ae24 p14.6 i/o b/ pu port 14 general purpose i/o line 6 ad22 i ebu address/data bus line 22 cout63 o1 ccu60 out102 o2 out102 line of gpta1 out102 o3 out102 line of ltca2 ad22 o ebu address/data bus line 22 ab30 p14.7 i/o b/ pu port 14 general purpose i/o line 7 ad23 i ebu address/data bus line 23 cc60 o1 ccu61 out103 o2 out103 line of gpta1 out103 o3 out103 line of ltca2 ad23 o ebu address/data bus line 23 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 69 v 1.1, 2014-05 ae23 p14.8 i/o b/ pu port 14 general purpose i/o line 8 ad24 i ebu address/data bus line 24 cc61 o1 ccu61 t3out o2 gpt120 out104 o3 out104 line of ltca2 ad24 o ebu address/data bus line 24 ac30 p14.9 i/o b/ pu port 14 general purpose i/o line 9 ad25 i ebu address/data bus line 25 cc62 o1 ccu61 t3out o2 gpt121 out105 o3 out105 line of ltca2 ad25 o ebu address/data bus line 25 ac29 p14.10 i/o b/ pu port 14 general purpose i/o line 10 ad26 i ebu address/data bus line 26 cout60 o1 ccu61 t6out o1 gpt120 out106 o3 out106 line of ltca2 ad26 o ebu address/data bus line 26 ad30 p14.11 i/o b/ pu port 14 general purpose i/o line 11 ad27 i ebu address/data bus line 27 cout61 o1 ccu61 t6out o1 gpt121 out107 o3 out107 line of ltca2 ad27 o ebu address/data bus line 27 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 70 v 1.1, 2014-05 ad29 p14.12 i/o b/ pu port 14 general purpose i/o line 12 ad28 i ebu address/data bus line 28 cout62 o1 ccu61 out108 o2 out108 line of gpta1 out108 o3 out108 line of ltca2 ad28 o ebu address/data bus line 28 ae30 p14.13 i/o b/ pu port 14 general purpose i/o line 13 ad29 i ebu address/data bus line 29 cout63 o1 ccu61 out109 o2 out109 line of gpta1 out109 o3 out109 line of ltca2 ad29 o ebu address/data bus line 29 ae29 p14.14 i/o b/ pu port 14 general purpose i/o line 14 ad30 i ebu address/data bus line 30 t3inc i gpt120 t3ind i gpt121 out110 o1 out110 line of gpta0 out110 o2 out110 line of gpta1 out110 o3 out110 line of ltca2 ad30 o ebu address/data bus line 30 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 71 v 1.1, 2014-05 af30 p14.15 i/o b/ pu port 14 general purpose i/o line 15 ad31 i ebu address/data bus line 31 t3eudc i gpt120 t3eudd i gpt121 out111 o1 out111 line of gpta0 out111 o2 out111 line of gpta1 out111 o3 out111 line of ltca2 ad31 o ebu address/data bus line 31 port 15 aj26 p15.0 i/o b/ pu port 15 general purpose i/o line 0 t4inc i gpt120 t4ind i gpt121 ccpos2b i ccu60 reserved o1 - reserved o2 - reserved o3 - cs0 o chip select output line 0 ak26 p15.1 i/o b/ pu port 15 general purpose i/o line 1 t4eudc i gpt120 t4eudd i gpt121 ccpos2b i ccu61 reserved o1 - reserved o2 - reserved o3 - cs1 o chip select output line 1 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 72 v 1.1, 2014-05 aj25 p15.2 i/o b/ pu port 15 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - cs2 o chip select output line 2 ak24 p15.3 i/o b/ pu port 15 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - cs3 o chip select output line 3 aj17 p15.4 i/o b/ pu port 15 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - bc0 o byte control line 0 ak18 p15.5 i/o b/ pu port 15 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - bc1 o byte control line 1 aj18 p15.6 i/o b/ pu port 15 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - bc2 o byte control line 2 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 73 v 1.1, 2014-05 ak19 p15.7 i/o b/ pu port 15 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - bc3 o byte control line 3 ak25 p15.8 i/o b/ pu port 15 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - rd o read control line aj27 p15.9 i/o b/ pu port 15 general purpose i/o line 9 reserved o1 - reserved o2 - reserved o3 - rd/wr o write control line aj28 p15.10 i/o b/ pu port 15 general purpose i/o line 10 reserved o1 - reserved o2 - reserved o3 - adv o address valid output aj24 p15.11 i/o b/ pu port 15 general purpose i/o line 11 wait i wait input for inser ting wait-states reserved o1 - reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 74 v 1.1, 2014-05 ak20 p15.12 i/o b/ pu port 15 general purpose i/o line 12 reserved o1 - reserved o2 - reserved o3 - mr/w o motorola-style read/write control signal ak29 p15.13 i/o b/ pu port 15 general purpose i/o line 13 reserved o1 - reserved o2 - reserved o3 - baa o burst address advance output ag30 p15.14 i/o b/ pu port 15 general purpose i/o line 14 bfclki i burst flash clock input (clock feedback). reserved o1 - reserved o2 - reserved o3 - ah30 p15.15 i/o b/ pu port 15 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - bfclko o burst mode flash clock output (non- differential) port 16 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 75 v 1.1, 2014-05 ak17 p16.0 i/o b/ pu port 16 general purpose i/o line 0 hold i hold request input reserved o1 - reserved o2 - reserved o3 - aj19 p16.1 i/o b/ pu port 16 general purpose i/o line 1 hlda i hold acknowledge input reserved o1 - reserved o2 - reserved o3 - hlda o hold acknowledge output ak28 p16.2 i/o b/ pu port 16 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - breq o bus request output aj20 p16.3 i/o b/ pu port 16 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - cscomb o combined chip select output ak23 p16.4 i/o b/ pu port 16 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - ras o row address select/strobe table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 76 v 1.1, 2014-05 aj23 p16.5 i/o b/ pu port 16 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - cas o column address select/strobe ag29 p16.6 i/o b/ pu port 16 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - ddrclk o double data rate flash clock af29 p16.7 i/o b/ pu port 16 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - ddrclkn o inverted double data rate flash clock ak27 p16.8 i/o b/ pu port 16 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - cke o inverted double data rate flash clock w29 p16.9 i/o b/ pu port 16 general purpose i/o line 9 dqs0 i data strobe signal 0 reserved o1 - reserved o2 - reserved o3 - dqs0 o data strobe signal 0 table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 77 v 1.1, 2014-05 y29 p16.10 i/o b/ pu port 16 general purpose i/o line 10 dqs1 i data strobe signal 1 reserved o1 - reserved o2 - reserved o3 - dqs1 o data strobe signal 1 aa29 p16.11 i/o b/ pu port 16 general purpose i/o line 11 dqs2 i data strobe signal 2 reserved o1 - reserved o2 - reserved o3 - dqs2 o data strobe signal 2 ab29 p16.12 i/o b/ pu port 16 general purpose i/o line 12 dqs3 i data strobe signal 3 reserved o1 - reserved o2 - reserved o3 - dqs3 o data strobe signal 3 port 17 y10 p17.0 i d / s port 17 general purpose i line 0 4) sent0 i sent digital input 0 an8 i analog input : adc0.ch8 5) y9 p17.1 i d / s port 17 general purpose i line 1 4) sent1 i sent digital input 1 an9 i analog input : adc0.ch9 5) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 78 v 1.1, 2014-05 w10 p17.2 i d / s port 17 general purpose i line 2 4) sent2 i sent digital input 2 an10 i analog input : adc0.ch10 5) w9 p17.3 i d / s port 17 general purpose i line 3 4) sent3 i sent digital input 3 an11 i analog input : adc0.ch11 5) w7 p17.4 i d / s port 17 general purpose i line 4 4) sent4 i sent digital input 4 an12 i analog input : adc0.ch12 5) w6 p17.5 i d / s port 17 general purpose i line 5 4) sent5 i sent digital input 5 an13 i analog input : adc0.ch13 5) v7 p17.6 i d / s port 17 general purpose i line 6 4) sent6 i sent digital input 6 an14 i analog input : adc0.ch14 5) v6 p17.7 i d / s port 17 general purpose i line 7 4) sent7 i sent digital input 7 an15 i analog input : adc0.ch15 5) ad9 p17.8 i d / s port 17 general purpose i line 8 4) sent0 i sent digital input 0 an36 i analog input : adc2.ch4 5) ae9 p17.9 i d / s port 17 general purpose i line 9 4) sent1 i sent digital input 1 an37 i analog input : adc2.ch5 5) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 79 v 1.1, 2014-05 ad10 p17.10 i d / s port 17 general purpose i line 10 4) sent2 i sent digital input 2 an38 i analog input : adc2.ch6 5) ae10 p17.11 i d / s port 17 general purpose i line 11 4) sent3 i sent digital input 3 an39 i analog input : adc2.ch7 5) aa11 p17.12 i d / s port 17 general purpose i line 12 4) sent4 i sent digital input 4 an40 i analog input : adc2.ch8 5) ab11 p17.13 i d / s port 17 general purpose i line 13 4) sent5 i sent digital input 5 an41 i analog input : adc2.ch9 5) aa12 p17.14 i d / s port 17 general purpose i line 14 4) sent6 i sent digital input 6 an42 i analog input : adc2.ch10 5) ab12 p17.15 i d / s port 17 general purpose i line 15 4) sent7 i sent digital input 7 an43 i analog input : adc2.ch11 5) port 18 b11 p18.0 i/o a1+/ pu port 18 general purpose i/o line 0 mrst2b i ssc2 master receive input b (slave mode) mrst2 o1 ssc2 slave transmit output (master mode) reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 80 v 1.1, 2014-05 a11 p18.1 i/o a1+/ pu port 18 general purpose i/o line 1 mtsr2b i ssc2 slave receive input b (slave mode) mrstg2b i ssc guardian 2 master receive input b (master mode) mtsr2 o1 ssc2 master transmit output (master mode) 3) reserved o2 - reserved o3 - b10 p18.2 i/o a1+/ pu port 18 general purpose i/o line 2 sclk2b i ssc2 input sclk2 o1 ssc2 output reserved o2 - reserved o3 - a10 p18.3 i/o a1+/ pu port 18 general purpose i/o line 3 slso20 o1 ssc2 output reserved o2 - reserved o3 - b9 p18.4 i/o a1+/ pu port 18 general purpose i/o line 4 slso21 o1 ssc2 output reserved o2 - reserved o3 - a9 p18.5 i/o a1+/ pu port 18 general purpose i/o line 5 slso22 o1 ssc2 output reserved o2 - reserved o3 - table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 81 v 1.1, 2014-05 b8 p18.6 i/o a1+/ pu port 18 general purpose i/o line 6 slso23 o1 ssc2 output reserved o2 - reserved o3 - a8 p18.7 i/o a1+/ pu port 18 general purpose i/o line 7 slso24 o1 ssc2 output reserved o2 - reserved o3 - analog input port aa9 an0 i d analog input 0: adc0.ch0 5) ae7 an1 i d analog input 1: adc0.ch1 5) ad7 an2 i d analog input 2: adc0.ch2 5) ad6 an3 i d analog input 3: adc0.ch3 5) ac7 an4 i d analog input 4: adc0.ch4 5) ab7 an5 i d analog input 5: adc0.ch5 5) aa7 an6 i d analog input 6: adc0.ch6 5) aa10 an7 i d analog input 7: adc0.ch7 5) y10 an8 i s analog input 8: adc0.ch8, sent0 5) y9 an9 i s analog input 9: adc0.ch9, sent1 5) w10 an10 i s analog input 10: adc0.ch10, sent2 5) w9 an11 i s analog input 11: adc0.ch11, sent3 5) w7 an12 i s analog input 12: adc0.ch12, sent4 5) w6 an13 i s analog input 13: adc0.ch13, sent5 5) v7 an14 i s analog input 14: adc0.ch14, sent6 5) v6 an15 i s analog input 15: adc0.ch15, sent7 5) v10 an16 i d analog input 16: adc1.ch0 5) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 82 v 1.1, 2014-05 v9 an17 i d analog input 17: adc1.ch1 5) u10 an18 i d analog input 18: adc1.ch2 5) u9 an19 i d analog input 19: adc1.ch3 5) u7 an20 i d analog input 20: adc1.ch4 5) u6 an21 i d analog input 21: adc1.ch5 5) t7 an22 i d analog input 22: adc1.ch6 5) t6 an23 i d analog input 23: adc1.ch7 5) ab13 an24 i d analog input 24: adc1.ch8 5) ad13 an25 i d analog input 25: adc1.ch9 5) ae13 an26 i d analog input 26: adc1.ch10 5) aa14 an27 i d analog input 27: adc1.ch11 5) ab14 an28 i d analog input 28: adc1.ch12 5) ad14 an29 i d analog input 29: adc1.ch13 5) ae14 an30 i d analog input 30: adc1.ch14 5) aa15 an31 i d analog input 31: adc1.ch15 5) ab9 an32 i d analog input 32: adc2.ch0 5) ad8 an33 i d analog input 33: adc2.ch1 5) ae8 an34 i d analog input 34: adc2.ch2 5) aa13 an35 i d analog input 35: adc2.ch3 5) ad9 an36 i s analog input 36: adc2.ch4, sent0 5) ae9 an37 i s analog input 37: adc2.ch5, sent1 5) ad10 an38 i s analog input 38: adc2.ch6, sent2 5) ae10 an39 i s analog input 39: adc2.ch7, sent3 5) aa11 an40 i s analog input 40: adc2.ch8, sent4 5) ab11 an41 i s analog input 41: adc2.ch9, sent5 5) aa12 an42 i s analog input 42: adc2.ch10, sent6 5) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 83 v 1.1, 2014-05 ab12 an43 i s analog input 43: adc2.ch11, sent7 5) ac6 an44 i d analog input 44: adc2.ch12 5) ab6 an45 i d analog input 45: adc2.ch13 5) aa6 an46 i d analog input 46: adc2.ch14 5) ab10 an47 i d analog input 47: adc2.ch15 5) w2 an48 i d analog input 48: adc3.ch0 5) w1 an49 i d analog input 49: adc3.ch1 5) aa2 an50 i d analog input 50: adc3.ch2 5) aa1 an51 i d analog input 51: adc3.ch3 5) ab2 an52 i d analog input 52: adc3.ch4 5) ab1 an53 i d analog input 53: adc3.ch5 5) ac2 an54 i d analog input 54: adc3.ch6 5) ac1 an55 i d analog input 55: adc3.ch7 5) ad2 an56 i d analog input 56: adc3.ch8 5) ad1 an57 i d analog input 57: adc3.ch9 5) ae2 an58 i d analog input 58: adc3.ch10 5) ae1 an59 i d analog input 59: adc3.ch11 5) af2 an60 i d analog input 60: adc3.ch12 5) af1 an61 i d analog input 61: adc3.ch13 5) ag2 an62 i d analog input 62: adc3.ch14 5) ag1 an63 i d analog input 63: adc3.ch15 5) aj5 an64 i d analog input 64: fadc_fadin0p 6) ak5 an65 i d analog input 65: fadc_fadin0n 6) aj6 an66 i d analog input 66: fadc_fadin1p 6) ak6 an67 i d analog input 67: fadc_fadin1n 6) aj7 an68 i d analog input 68: fadc_fadin2p 6) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 84 v 1.1, 2014-05 ak7 an69 i d analog input 69: fadc_fadin2n 6) aj8 an70 i d analog input 70: fadc_fadin3p 6) ak8 an71 i d analog input 71: fadc_fadin3n 6) system i/o l24 porst ipd power-on reset input m24 esr0 i/o a2 external system request reset input 0 default configuration du ring and after reset is open-drain driver. the driver drives low during power-on reset. m25 esr1 i/o a2/ pd external system request reset input 1 n25 tck i pd jtag module clock input dap0 i device access port line 0 p22 tdi i a2/ pu jtag module serial data input brkin i ocds break input (alternate output) brkout o ocds break output (alternate input) m22 testmode ipu test mode select input p21 tms i a2/ pd jtag module state machine control input dap1 i/o device access port line 1 n24 trst ipd jtag module reset/enable input r25 xtal1 i main oscillator/pll/clock generator input r24 xtal2 o main oscillator/pll/clock generator output n22 tdo o a2/ pu jtag module serial data output brkin i ocds break input (alternate input) brkout o ocds break output (alternate output) dap2 o device access port line 2 power supply table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 85 v 1.1, 2014-05 y7 v ddm -- adc analog part power supply (3.3v - 5v) y1, y2, y6 v ssm -- adc analog part ground ae11 v aref0 -- adc0 reference voltage ae12 v agnd0 -- adc0 reference ground ad11 v aref1 -- adc1 reference voltage ak9 v agnd1 -- adc1 reference ground ad12 v aref2 -- adc2 reference voltage aj10 v agnd2 -- adc2 reference ground aj9 v aref3 -- adc3 reference voltage ak10 v agnd3 -- adc3 reference ground ab15 v faref -- fadc reference voltage ad15 v fagnd -- fadc reference ground ab16 v ddmf -- fadc analog part power supply (3.3v) aa16 v ddaf -- fadc analog part logic power supply (1.3v) ae15, aj11, ak11 v ssmf -- fadc analog part ground v ssaf -- fadc analog part logic ground r10, t21 v ddfl3 -- flash power supply (3.3v) r30, r29, p25 v ssosc -- main oscillator ground v ss -- digital ground p24 v ddosc -- main oscillator power supply (1.3v) r21 v ddosc3 -- main oscillator power supply (3.3v) r22 v ddpf -- e-ray pll power supply (1.3v) t22 v ddpf3 -- e-ray pll power supply (3.3v) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 86 v 1.1, 2014-05 aj30, ah29, ad25, ac24, aa22, y21 v dd -- digital core powe r supply (1.3v) w18, w13, v19, v12, n19, n12, m18, m13 v dd -- digital core power su pply (1.3v, center balls) ak15, aj15, ad16, t2, t1, r7, g23, g15, g8, f24, f7, b28, a29, b16, a16, b3, a2 v ddp -- port power supply (3.3v) ak21, aj21, ad22, u24, u25, u29, u30, c30 v ddebu -- ebu port power supply (1.8 - 2.5v - 3.3v) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 87 v 1.1, 2014-05 t9, t10 v ddsb -- emulation stand-by sram power supply (1.3v) (emulati on device only) note: this pin is n.c. in a productive device. ak16, aj16, ae16, r6, r2, r1, f15, k10, k21, j22, j9, g24, g7, f25, b29, b15, b2, a30, a15 v ssp -- digital ground ak22, aj22, ae22, t30, t29, t25, t24, b30 v ss -- digital ground table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 88 v 1.1, 2014-05 w17, w16, w15, w14, , v17, v16, v15, v14 v ss -- digital ground (center balls) n17, n16, n15, n14, , m17, m16, m15, m14 v ss -- digital ground (center balls cont?d) u19, u18, u16, u15, u13, u12, p13, p12, p19, p18, p16, p15, v ss -- digital ground (center balls cont?d) r19, r18, r17, r16, r15, r14, r13, r12 v ss -- digital ground (center balls cont?d) table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 89 v 1.1, 2014-05 t19, t18, t17, t16, t15, t14, t13, t12 v ss -- digital ground (center balls cont?d) ak30, aj29, ae25, ad24, ab22, aa21 v ss -- digital ground (center balls cont?d) a1, a3, a4, a5, a14, a17, a23, a24, a25, a26 n.c. - - not connected. these pins are reserved for future extension and shall not be connected externally. b1, b4, b5, b14, b17, b23, b24, b25, b26 n.c. - - not connected. these pins are reserved for future extension and shall not be connected externally. table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 90 v 1.1, 2014-05 c1, c2, c29, d1, d2, e1, e2, f1, f2, f6, g1, g2, n1, n2 n.c. - - not connected. these pins are reserved for future extension and shall not be connected externally. u1, u2, v1, v2, ae6, ah1, ah2, aj1, aj2, aj3 n.c. - - not connected. these pins are reserved for future extension and shall not be connected externally. aj4, aj12, ak1, ak2, ak3, ak4, ak12, ak13 n.c. - - not connected. these pins are reserved for future extension and shall not be connected externally. 1) only applicable in TC1798ed. reserved in TC1798pd. 2) only available for sak-TC1798f-512f300el, sak-TC1798f-512f300ep, and sak-TC1798s-512f300ep. 3) the mtsr output of sscx is overlayed with the mrstg input of the related sscgx 4) analog input overlayed with a sent digitial input. the re lated port logic is used configure the input as either analog input (default after reset) or digital input. the related port logic supports only the port input features as the connected pads are input pads only. table 2 pin definitions and functions (pg-lfbga- 516 package) (cont?d) pin symbol ctrl. type function
TC1798 pinningTC1798 pin configuration data sheet 91 v 1.1, 2014-05 legend for table 2 column ? ctrl. ?: i = input (for gpio port lines with iocr bit field selection pcx = 0xxx b ) o = output o0 = output with iocr bit field selection pcx = 1x00 b o1 = output with iocr bit field selection pcx = 1x01 b (alt1) o2 = output with iocr bit field selection pcx = 1x10 b (alt2) o3 = output with iocr bit field selection pcx = 1x11(alt3) column ? type ?: a1 = pad class a1 (lvttl) a1+ = pad class a1+ (lvttl) a2 = pad class a2 (lvttl) b = pad class b (lvttl) f = pad class f (lvds/cmos) d = pad class d (adc) s = pad class d (adc) / pad class s(sent) pu = with pull-up device connected during reset (porst = 0) pd = with pull-down device connected during reset (porst = 0) tr = tri-state during reset (porst = 0) 5) ioz1 valid for this pin is the parameter with overlayed = no in the adc parameter table. 6) ioz1 valid for this pin is the parameter with overlayed = yes in the adc parameter table.
TC1798 identification registers data sheet 92 v 1.1, 2014-05 4 identification registers the identification registers uniq uely identify the whole device. table 3 sak-TC1798f-512f300el identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 0700 9802 h f000 0640 h ab scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0000 h f000 0648 h ab table 4 sak-TC1798f-512f300ep identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 8700 9802 h f000 0640 h ab scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0000 h f000 0648 h ab table 5 sak-TC1798n-512f300ep identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 8700 b002 h f000 0640 h ab scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0000 h f000 0648 h ab table 6 sak-TC1798s-512f300ep identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 8700 ac02 h f000 0640 h ab
TC1798 identification registers data sheet 93 v 1.1, 2014-05 scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0000 h f000 0648 h ab table 6 sak-TC1798s-512f300ep identification registers (cont?d) short name value address stepping
TC1798 electrical parametersgeneral parameters data sheet 94 v 1.1, 2014-05 5 electrical parameters this specification provides all elec trical parameters of the TC1798. 5.1 general parameters 5.1.1 parameter interpretation the parameters listed in this section partly represent the characteristics of the TC1798 and partly its requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the TC1798 and must be regarded for a system design. ? sr such parameters indicate s ystem r equirements which must provided by the microcontroller system in which the TC1798 designed in.
TC1798 electrical parametersgeneral parameters data sheet 95 v 1.1, 2014-05 5.1.2 pad driver and pad classes summary this section gives an overview on the different pad driver classes and its basic characteristics. more details (mainly dc parameters) are defined in the section 5.2.1 . table 7 pad driver and pad classes overview class power supply type sub class speed grade 1) 1) these values show typical application configurations for the pad. complete and detailed pad parameters are available in the individual pad parameter table on the following pages. load 1) leakage 150oc 1) termination a 3.3 v lvttl i/o, lvttl outputs a1 (e.g. gpio) 6 mhz 100 pf 500 na no a1+ (e.g. serial i/os) 25 mhz 50 pf 1 aseries termination recommended a2 (e.g. serial i/os) 40 mhz 50 pf 3 aseries termination recommended b 3.3 v 2) 2) supplied via v ddebu . lvttl i/o 75 mhz 35 pf 6 aseries termination recommended 2.5 v 2) 75 mhz 35 pf 1.8 v 2) f 3.3 v lvds ? 50 mhz ?? parallel termination, 100 10% 3) 3) in applications where the lvds pins are not used (d isabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%. cmos ? 6 mhz 50 pf ? de 5v adc ? ? ? ? i 3.3 v lvttl (input only) ????
TC1798 electrical parametersgeneral parameters data sheet 96 v 1.1, 2014-05 5.1.3 absolute maximum ratings stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 8 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max. storage temperature t st sr -65 ? 150 c? voltage at 1.3 v power supply pins with respect to v ss v dd sr ? ? 2.0 v ? voltage at 3.3 v power supply pins with respect to v ss v ddp sr ??4.33 v? voltage at 5 v power supply pins with respect to v ss v ddm sr ? ? 7.0 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.7 ? v ddp + 0.5 or max. 4.33 v whatever is lower voltage on any class d analog input pin with respect to v agnd v ain v arefx sr -0.6 ? 7.0 v ? voltage on any shared class d analog input pin with respect to v ssaf , if the fadc is switched through to the pin. v ainf v faref sr -0.6 ? 7.0 v ? voltage on any shared class d analog input pin with respect to v ssaf , if the fadc is switched through to the pin. v ainf sr -0.5 ? 7.0 v ? input current on any pin during overload condition 1) i in -10 ? +10 ma 2)
TC1798 electrical parametersgeneral parameters data sheet 97 v 1.1, 2014-05 absolute maximum sum of all input circuit currents for one port group during overload condition 3) i in -25 ? +25 ma absolute maximum sum of all input circuit currents during overload condition i in -200 ? 200 ma 1) this parameter is an absolute maximum rating. expos ure to absolute maximum ratings for extended periods of time may damage the device. 2) refers to possibility of current caused degradation, where the voltages in overload do not violate the normal operating conditions. in case that the overvoltages violate the normal operating conditions, the reliability considerations caused by ov ervoltage apply independently, as described in this document. 3) the port groups are defined in table 13 . table 8 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max.
TC1798 electrical parametersgeneral parameters data sheet 98 v 1.1, 2014-05 5.1.4 pin reliability in overload when receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own io power supplies specification. table 9 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: ? full operation life-time (24000 h) is not exceeded ? operating conditions are met for ? pad supply levels ( v ddp or v ddm ) ? temperature if a pin current is out of the operating conditions but within the overload parameters, then the parameters functionality of this pin as stated in the operat ing conditions can no longer be guaranteed. operat ion is still possible in mo st cases but with relaxed parameters. note: an overload condition on one or more pins does not require a reset. note: fadc input pins count as analog pin as they are overlayed with an adc pins. table 9 overload parameters parameter symbol values unit note / test con dition min. typ. max. input current on any digital pin during overload condition except lvds pins i in -5 ? +5 ma input current on lvds pins i inlvds -3 ? +3 ma absolute sum of all input circuit currents for one port group during overload condition 1) 1) the port groups are defined in table 13 . i ing -20 ? +20 ma input current on analog pins i inana -3 ? +3 ma absolute sum of all analog input currents for analog inputs during overload condition i insa -45 ? +45 ma absolute sum of all input circuit currents during overload condition i ins -100 ? 100 ma
TC1798 electrical parametersgeneral parameters data sheet 99 v 1.1, 2014-05 note: a series resistor at the pin to limit the current to the maxi mum permitted overload current is sufficient to handle failure situ ations like short to battery without having any negative reliability impact on the operational life-time. table 10 pn-junction characteris itics for positive overload pad type i in =3ma i in =5ma a1 / a1+ / f u in = v ddp +0.6v u in = v ddp +0.7v a2 u in = v ddp +0.5v u in = v ddp +0.6v lvds u in = v ddp +0.7v - d u in = v ddm +0.6v - s u in = v ddm +0.6v - table 11 pn-junction characterisitics for negative overload pad type i in =-3ma i in =-5ma a1 / a1+ / f u in = v ss -0.6v u in = v ss -0.7v a2 u in = v ss -0.5v u in = v ss -0.6v lvds u in = v ss -0.7v - d u in = v ssm -0.6v - s u in = v ssm -0.6v -
TC1798 electrical parametersgeneral parameters data sheet 100 v 1.1, 2014-05 5.1.5 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation and reliability of t he TC1798. all parameters specif ied in the following tables refer to these operating conditions, unless otherwise noticed. digital supply voltages applied to the tc179 8 must be static regulated voltages which allow a typical voltage swing of 5 %. all parameters specified in the following tables ( table 14 and following) refer to these operating conditions ( table 12 ), unless otherwise noticed in the note / test condition column. the extended range operating conditions did not increase area of validity of the parameters defined in table 10 and later. table 12 operating conditions parameters parameter symbol values unit note / test condition min. typ. max. overload coupling factor for analog inputs, negative k ovan cc ?? 0.0001 i ov 0ma; i ov -2 ma; analog pad= 5.0 v overload coupling factor for analog inputs, positive k ovap cc ?? 0.0000 1 i ov 3ma; i ov 0ma; analog pad= 5.0 v cpu frequency f cpu sr ?? 300 mhz modulated f cpu f cpu_mod ulated sr ?? 300- 2*ma 1) mhz fpi bus frequency f fpi sr ?? 100 mhz modulated f fpi f fpi_modul ated sr ?? 100- 2*ma 1) mhz fsi frequency f fsi sr ?? 150 mhz modulated f fsi f fsi_modul ated sr ?? 150- 2*ma 1) mhz pcp frequency f pcp sr ?? 200 mhz modulated f pcp f pcp_mod ulated sr ?? 200- 2*ma 1) mhz sri frequency f sri sr ?? 300 mhz
TC1798 electrical parametersgeneral parameters data sheet 101 v 1.1, 2014-05 modulated f sri f sri_modul ated sr ?? 300- 2*ma 1) mhz inactive device pin current i id sr -1 ? 1 ma all power supply voltages v ddx = 0 short circuit current of digital outputs 2) i sc sr -5 ? 5ma absolute sum of short circuit currents of the device i sc_d cc ?? 100 ma absolute sum of short circuit currents per pin group i sc_pg cc ?? 20 ma ambient temperature t a sr -40 ? 125 c junction temperature t j sr -40 ? 150 c core supply voltage v dd sr 1.235 1.3 1.365 3) v for duration limitation see section 5.1.5.1 ebu supply voltage v ddebu sr 3.135 3.3 3.465 5) v for duration limitation see section 5.1.5.1 2.375 2.5 2.625 v 1.71 1.8 1.89 v flash supply voltage 3.3v v ddfl3 sr 3.135 3.3 3.63 5) v for duration limitation see section 5.1.5.1 adc analog supply voltage v ddm sr 3.135 5 5.5 4) v oscillator core supply voltage v ddosc sr 1.235 1.3 1.43 3) v for duration limitation see section 5.1.5.1 oscillator 3.3v supply voltage v ddosc3 sr 3.135 3.3 3.63 5) v for duration limitation see section 5.1.5.1 table 12 operating conditions parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersgeneral parameters data sheet 102 v 1.1, 2014-05 5.1.5.1 extended range operating conditions the following extended operati ng conditions are defined: ? 1.3v + 5% < v dd / v ddosc / v ddpf / v ddaf <1.3v + 7.5% (overvoltage condition): digital supply voltage for io pads v ddp sr 3.135 3.3 3.63 5) v for duration limitation see section 5.1.5.1 e-ray pll core voltage supply v ddpf sr 1.235 1.3 1.43 3) v for duration limitation see section 5.1.5.1 e-ray pll 3.3v supply v ddpf3 sr 3.135 3.3 3.63 5) v for duration limitation see section 5.1.5.1 vddp voltage to ensure defined pad states 6) v ddppa cc 0.65 ?? v digital ground voltage v ss sr 0 ?? v analog ground voltage for v ddm v ssm sr -0.1 0 0.1 v analog core supply v ddaf sr 1.235 1.3 1.365 3) v for duration limitation see section 5.1.5.1 fadc / adc analog supply voltage v ddmf sr 3.135 3.3 3.47 5) v for duration limitation see section 5.1.5.1 analog ground voltage for v ddmf v ssaf sr -0.1 0 0.1 v 1) ma equals the modulation amplitude in percenta ge times the configured pll clock out frequency. 2) applicable for digital outputs. 3) voltage overshoot to 1.7v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 4) voltage overshoot to 6.5v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 5) voltage overshoot to 4.0v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) this parameter is valid under the assumption the porst signal is constantly at low level during the power- up/power-down of v ddp . table 12 operating conditions parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersgeneral parameters data sheet 103 v 1.1, 2014-05 ? limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. ? 1.3v + 7.5% < v dd / v ddosc / v ddpf / v ddaf <1.3v + 10% (overvoltage condition): ? limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. ? v ddp / v ddosc3 / v ddpf3 / v ddfl3 / v ddmf / v ddebu <3.3v 10% ? 3.3v + 5% < v ddp / v ddosc3 / v ddpf3 / v ddfl3 / v ddmf / v ddebu <3.3v + 10% (overvoltage condition): limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. table 13 pin groups for overload / short-circuit current sum parameter group pins 1 p2.[4:2], p6.[6:9] 2 p6.[5:4], p6.[11:10] 3 p6.[15:12] 4 p8.[5:0] 5 p8.[7:6], p1.[15:13] 6 p1.5, p1.[11:8] 7 p1.[4:2], p1.6, p1.12 8 p1.[1:0], p7.[2:0] 9 p7.[7:3] 10 p4.[6:0] 11 p4.[10:7] 12 p4.[15:11] 13 p10.[5:0] 14 p15.[7:4], p16.[1:0] 15 p15.3, p15.[12:11], p16.[5:3] 16 p15.[2:0], p15.[9:8], p16.2, p16.8 17 p15.10, p15.[15:13], p16.[7:6] 18 p14.[15:12] 19 p14.[11:8], p16.12 20 p14.[7:3], p16.11 21 p13.15, p14.[2:0]
TC1798 electrical parametersgeneral parameters data sheet 104 v 1.1, 2014-05 22 p13.[14:11] 23 p13.[10:8], p16.10 24 p13.[7:4], p16.9 25 p12.5, p13.[3:0] 26 p12.[4:0] 27 p11.[15:11] 28 p11.[10:6] 29 p11.[5:2] 30 p11.[1:0], p12.[7:6] 31 p9.10, p9.14 32 p9.7, p9.13 33 p9.[4:2], p9.6 34 p9.1, p9.5, p9.[9:8] 35 p9.0, p9.[12:11] 36 p5.[11:8] 37 p5.6, p5.[15:12] 38 p5.0, p5.[5:2], p5.7 39 p3.[5:0], p5.1 40 p3.[12:6] 41 p0.[3:0], p3.[15:13] 42 p0.[11:4] 43 p0.[14:12] 44 p0.15, p18.[5:0] 45 p2.[15:11], p18.[7:6] 46 p2.[10:5] table 13 pin groups for overload / short-circuit current sum parameter (cont?d) group pins
TC1798 electrical parametersdc parameters data sheet 105 v 1.1, 2014-05 5.2 dc parameters 5.2.1 input/output pins table 14 standard_pads parameters parameter symbol values unit note / test condition min. typ. max. pin capacitance (digital inputs/outputs) c io cc ?? 10 pf t a =25c; f =1mhz pull-down current | i pdl | cc ?? 150 a v i 0.6 x v ddp v 10 ?? a v i 0.36 x v ddp v pull-up current | i puh | cc 10 ?? a v i 0.6 x v ddp v ?? 100 a v i 0.36 x v ddp v spike filter always blocked pulse duration t sf1 cc ?? 10 ns only porst pin spike filter pass-through pulse duration t sf2 cc 100 ?? ns only porst pin table 15 standard_pads class_a1 parameter symbol values unit note / test condition min. typ. max. input hysteresis for a1 pads 1) hysa1 cc 0.1 x v ddp ?? v input leakage current class a1 i oza1 cc -500 ? 500 na v i 0v; v i v ddp v ratio vil/vih, a1 pads v ila1 / v iha1 cc 0.6 ??
TC1798 electrical parametersdc parameters data sheet 106 v 1.1, 2014-05 on-resistance of the class a1 pad, weak driver r dsonw cc ? 450 600 ohm i oh >-0.5ma; p_mos ? 210 340 ohm i ol <0.5ma; n_mos on-resistance of the class a1 pad, medium driver r dsonm cc ?? 155 ohm i oh >2ma; p_mos ?? 110 ohm i ol <2ma; n_mos fall time,pad type a1 t fa1 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 15 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 107 v 1.1, 2014-05 rise time, pad type a1 t ra1 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage class a1 pads v iha1 sr 0.6 x v ddp ? min(v ddp + 0.3,3.6 ) v input low voltage class a1 pads v ila1 sr -0.3 ? 0.36 x v ddp v table 15 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 108 v 1.1, 2014-05 output voltage high class a1 pads v oha1 cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak output voltage low class a1 pads v ola1 cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 500 a; pin out driver= weak 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. table 16 standard_pads class_a1+ parameter symbol values unit note / test condition min. typ. max. input hysteresis for a1+ pads 1) hysa1 + cc 0.1 x v ddp ?? v input leakage current class a1+ i oza1+ cc -1000 ? 1000 na on-resistance of the class a1+ pad, weak driver r dsonw cc ? 450 600 ohm i oh >-0.5ma; p_mos ? 210 340 ohm i ol <0.5ma; n_mos table 15 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 109 v 1.1, 2014-05 on-resistance of the class a1+ pad, medium driver r dsonm cc ?? 155 ohm i oh >2ma; p_mos ?? 110 ohm i ol <2ma; n_mos on-resistance of the class a1+ pad, strong driver r dson1+ cc ?? 100 ohm i oh >2ma; p_mos ?? 80 ohm i ol <2ma; n_mos fall time, pad type a1+ t fa1+ cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 28 ns c l =50pf; edge= slow ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 16 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 110 v 1.1, 2014-05 rise time, pad type a1+ t ra1+ cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 28 ns c l =50pf; edge= slow ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage, class a1+ pads v iha1+ sr 0.6 x v ddp ? min(v ddp + 0.3,3.6 ) v input low voltage class a1+ pads v ila1+ sr -0.3 ? 0.36 x v ddp v ratio vil/vi h, a1+ pads v ila1+ / v iha1+ cc 0.6 ?? table 16 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 111 v 1.1, 2014-05 output voltage high class a1+ pads v oha1+ cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= strong 2.4 ?? v i oh -2 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= strong v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak output voltage low class a1+ pads v ola1+ cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 2 ma; pin out driver= strong ?? 0.4 v i ol 500 a; pin out driver= weak 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. table 16 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 112 v 1.1, 2014-05 table 17 standard_pads class_a2 parameter symbol values unit note / test condition min. typ. max. input hysteresis for a2 pads 1) hysa2 cc 0.1 x v ddp ?? v input leakage current class a2 i oza2 cc -6000 ? 6000 na v i < v ddp / 2 - 1v; v i > v ddp / 2 + 1 v; v i 0v; v i v ddp v -3000 ? 3000 na v i > v ddp / 2 - 1v; v i < v ddp / 2 + 1 v ratio vil/vih, a2 pads v ila2 / v iha2 cc 0.6 ?? on-resistance of the class a2 pad, weak driver r dsonw cc ? 450 600 ohm i oh >-0.5ma; p_mos ? 210 340 ohm i ol <0.5ma; n_mos on-resistance of the class a2 pad, medium driver r dsonm cc ?? 155 ohm i oh >2ma; p_mos ?? 110 ohm i ol <2ma; n_mos on-resistance of the class a2 pad, strong driver r dson2 cc ?? 28 ohm i oh >2ma; p_mos ?? 22 ohm i ol <2ma; n_mos
TC1798 electrical parametersdc parameters data sheet 113 v 1.1, 2014-05 fall time, pad type a2 t fa2 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 7ns c l =50pf; edge= medium ; pin out driver= strong ?? 10 ns c l =50pf; edge= medium- minus ; pin out driver= strong ?? 3.7 ns c l =50pf; edge= sharp ; pin out driver= strong ?? 5ns c l =50pf; edge= sharp- minus ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 7.5 ns c l =100pf; edge= sharp ; pin out driver= strong ?? 140 ns c l = 150 pf; pin out driver= medium table 17 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 114 v 1.1, 2014-05 ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 17 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 115 v 1.1, 2014-05 rise time, pad type a2 t ra2 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 7.0 ns c l =50pf; edge= medium ; pin out driver= strong ?? 10 ns c l =50pf; edge= medium- minus ; pin out driver= strong ?? 3.7 ns c l =50pf; edge= sharp ; pin out driver= strong ?? 5ns c l =50pf; edge= sharp- minus ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 7.5 ns c l =100pf; edge= sharp ; pin out driver= strong ?? 140 ns c l = 150 pf; pin out driver= medium table 17 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 116 v 1.1, 2014-05 ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage, class a2 pads v iha2 sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low voltage class a2 pads v ila2 sr -0.3 ? 0.36 x v ddp v output voltage high class a2 pads v oha2 cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= strong 2.4 ?? v i oh -2 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= strong v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak table 17 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 117 v 1.1, 2014-05 output voltage low class a2 pads v ola2 cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 2 ma; pin out driver= strong ?? 0.4 v i ol 500 a; pin out driver= weak 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. table 18 standard_pads class_b parameter symbol values unit note / test condition min. typ. max. input hysteresis, b class pads 1) hysb cc 0.05 x v ddebu ?? v v ddebu =1.8v 0.08 x v ddebu ?? v v ddebu =2.5v 0.1 x v ddebu ?? v v ddebu =3.3v input leakage current, class b pads i ozb cc -3000 ? 3000 na v ddebu =1.8v; v i >0v; v i < v ddebu v -6000 ? 6000 na v i > 0v; v i > v ddebu /2 + 0.6 v; v i v ddebu v; v i v ddebu /2 - 0.6 v -3000 ? 3000 na v i > v ddebu /2 - 0.6 v; v i < v ddebu /2 + 0.6 v table 17 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 118 v 1.1, 2014-05 ratio between low and high input threshold v ilb / v ihb cc 0.6 ?? on-resistance of the class b pad, weak driver r dsonw cc ? 450 600 ohm i oh >-0.5ma; p_mos; v ddebu =3.3v ? 210 340 ohm i ol <0.5ma; n_mos; v ddebu =3.3v on-resistance of the class b pad, medium driver r dsonm cc ?? 155 ohm i oh >-2ma; p_mos; v ddebu =3.3v ?? 110 ohm i ol <2ma; n_mos; v ddebu =3.3v on-resistance of the class b pad, strong driver r dson2 cc ?? 28 ohm i oh >-2ma; p_mos; v ddebu =3.3v ?? 22 ohm i ol <2ma; n_mos; v ddebu =3.3v table 18 standard_pads class_b (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 119 v 1.1, 2014-05 fall time, class b pads; edge= sharp ; pin out driver= strong 2) t fb cc ?? 3.3 ns c l =20pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 5.0 ns c l =35pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 3.0 ns c l =35pf; v ddebu 2.375 ; v ddebu 2.625 ?? 2.5 ns c l =35pf; v ddebu 3.13 ; v ddebu 3.47 ?? 7.0 ns c l =50pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 4.0 ns c l =50pf; v ddebu 2.375 ; v ddebu 2.625 ?? 3.3 ns c l =50pf; v ddebu 3.13 ; v ddebu 3.47 ?? 12.0 ns c l =100pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 7.0 ns c l =100pf; v ddebu 2.375 ; v ddebu 2.625 ?? 6.0 ns c l =100pf; v ddebu 3.13 ; v ddebu 3.47 table 18 standard_pads class_b (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 120 v 1.1, 2014-05 rise time, class b pads; edge= sharp ; pin out driver= strong 2) t rb cc ?? 3.3 ns c l =20pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 5.0 ns c l =35pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 3.0 ns c l =35pf; v ddebu 2.375 ; v ddebu 2.625 ?? 3.0 ns c l =35pf; v ddebu 3.13 ; v ddebu 3.47 ?? 7.0 ns c l =50pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 4.0 ns c l =50pf; v ddebu 2.375 ; v ddebu 2.625 ?? 3.7 ns c l =50pf; v ddebu 3.13 ; v ddebu 3.47 ?? 12.0 ns c l =100pf; v ddebu 1.53 v; v ddebu 1.98 v ?? 7.0 ns c l =100pf; v ddebu 2.375 ; v ddebu 2.625 ?? 6.0 ns c l =100pf; v ddebu 3.13 ; v ddebu 3.47 input high voltage, class b pads v ihb cc 0.6 x v ddebu ? max(v ddebu + 0.3, 3.6) v table 18 standard_pads class_b (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 121 v 1.1, 2014-05 input low voltage, class b pads v ilb cc -0.3 ? 0.36 x v ddebu v output voltage high, class b pads v ohb cc v ddebu - 0.4 ?? v i oh -2 ma; output voltage low, class b pads v olb cc ?? 0.4 v i ol =2ma 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. 2) for non strong driver and sharp edge se ttings see the class a2 definitions. table 19 standard_pads class_f parameter symbol values unit note / test condition min. typ. max. input hysteresis f 1) hysf cc 0.05 x v ddp ?? v input leakage current class f i ozf cc -6000 ? 6000 na v i < v ddp / 2 - 1v; v i > v ddp / 2 + 1 v; v i 0v; v i v ddp v -3000 ? 3000 na v i > v ddp / 2 - 1v; v i < v ddp / 2 + 1 v ratio vil/ vih, f pads v ilf / v ihf cc 0.6 ?? on-resistance of the class f pad, medium driver r dsonm cc ?? 170 ohm i oh >-2ma; p_mos ?? 145 ohm i ol <2ma; n_mos fall time, pad type f, cmos mode t ff cc ?? 60 ns c l =50pf rise time, pad type f, cmos mode t rf cc ?? 60 ns c l =50pf table 18 standard_pads class_b (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 122 v 1.1, 2014-05 class s pad parameters are only valid for v ddm = 4.75 v to 5.25 v. input high voltage, pad class f, cmos mode v ihf sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low voltage, class f pads, cmos mode v ilf sr -0.3 ? 0.36 x v ddp v output high voltage, class f pads, cmos mode v ohf cc v ddp- 0.4 ?? v i oh -1.4 ma 2.4 ?? v i oh -2 ma output low voltage, class f pads, cmos mode v olf cc ?? 0.4 v i ol 2ma 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. table 20 standard_pads class_i parameter symbol values unit note / test condition min. typ. max. input hysteresis class i 1) 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. hysi cc 0.1 x v ddp ?? v input leakage current i ozi cc -1000 ? 1000 na ratio between low and high input threshold v ili / v ihi cc 0.6 ?? input high voltage, class i pins v ihi sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low voltage, class i pads v ili sr -0.3 ? 0.36 x v ddp v table 19 standard_pads class_f (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 123 v 1.1, 2014-05 table 21 standard_pads class_s parameter symbol values unit note / test condition min. typ. max. input hysteresis for class s pads 1) 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. hyss cc 0.3 ?? v input leakage current i ozs cc -300 ? 300 na input voltage high v ihs cc ?? 3.6 v input voltage low v ils cc 1.9 ?? v v ils delta 2) 2) v ilsd is implemented to ensure j2716 specification. it can?t be guaranteed that it suppresses switching due to external noise. v ilsd cc -50 ? 50 mv maximum input low state treshold variation over 1ms ( v ddp =consta nt) table 22 lvds_pa ds parameters parameter symbol values unit note / test condition min. typ. max. output impedance, pad class f, lvds mode r o cc 40 ? 140 ohm fall time, pad type lvds t fl cc ?? 2 ns termination 100 ? 1%; differential capacitance = 1 0 pf; input capacitance = 2 0pf
TC1798 electrical parametersdc parameters data sheet 124 v 1.1, 2014-05 rise time, pad type lvds t rl cc ?? 2 ns termination 100 ? 1%; differential capacitance = 1 0 pf; input capacitance = 2 0pf pad set-up time t set_lvd s cc ?? 13 s termination 100 ? 1% output differential voltage v od cc 150 ? 400 mv termination 100 ? 1% output voltage high, pad class f, lvds mode v oh cc ?? 1525 mv termination 100 ? 1% output voltage low, pad class f, lvds mode v ol cc 875 ?? mv termination 100 ? 1% output offset voltage v os cc 1075 ? 1325 mv termination 100 ? 1% table 22 lvds_pads parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 125 v 1.1, 2014-05 5.2.2 analog to digital converters (adcx) adc parameter are valid for v dd / ddaf = 1.235 v to 1.365 v; v ddm = 4.5 v to 5.5 v. table 23 adc parameters parameter symbol values unit note / test condition min. typ. max. switched capacitance at the analog voltage inputs 1) c ainsw cc ? 920pf total capacitance of an analog input c aintot cc ? 20 30 pf switched capacitance at the positive reference voltage input 2)3) c arefsw cc ? 15 30 pf total capacitance of the voltage reference inputs 2) c arefto t cc ? 20 40 pf differential non-linearity error 4)5)6)7) ea dnl cc -3 ? 3 lsb adc resolution= 12- bit 8) 9) gain error 4)5)6)7) ea gain cc -3.5 ? 3.5 lsb adc resolution= 12- bit 8) 9) integral non- linearity 4)5)7)7) ea inl cc -3 ? 3 lsb adc resolution= 12- bit 8) 9) ; adc = 0,1,2 -3 ? 3 lsb adc resolution= 12- bit 8) 9) adc3 and v ain v arefx - 0.15 v -15 ? 15 lsb adc resolution= 12- bit 8) 9) adc3 and v arefx - 0.15 v v ain < v arefx
TC1798 electrical parametersdc parameters data sheet 126 v 1.1, 2014-05 offset error 4)5)6)7) ea off cc -4 ? 4 lsb adc resolution= 12- bit 8) 9) converter clock f adc sr 4 ? 100 mhz f adc = f fpi internal adc clock f adci cc 1 ? 18 mhz adc0 1 ? 18 mhz adc1 1 ? 20 10) mhz adc2 1 ? 16 mhz adc3 charge consumption per conversion q conv cc 70 85 11) 100 pc charge needs to be provided via v aref0 table 23 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 127 v 1.1, 2014-05 input leakage at analog inputs 12) i oz1 cc -100 ? 500 na v i v ddm v; v i 0.97 x v ddm v; overlayed= no -100 ? 600 na v i 0.97 x v ddm v; v i v ddm v; overlayed= yes -500 ? 100 na v i 0.03 x v ddm v; v i 0v; overlayed= no -600 ? 100 na v i 0.03 x v ddm v; v i 0v; overlayed= yes -100 ? 200 na v i > 0.03 x v ddm v; v i < 0.97 x v ddm v; overlayed= no -100 ? 300 na v i < 0.97 x v ddm v; v i > 0.03 x v ddm v; overlayed= yes input leakage current at v arefx i oz2 cc -1 ? 1 a v arefx 0v; v arefx v ddm v input leakage current at v agndx i oz3 cc -1 ? 1 a v agndx 0v; v agndx v ddm v on resistance of the transmission gates in the analog voltage path r ain cc ? 900 1500 ohm on resistance for the adc test (pull down for ain7) r ain7t cc 180 550 900 ohm table 23 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 128 v 1.1, 2014-05 resistance of the reference voltage input path r aref cc ? 500 1000 ohm sample time t s cc 2 ? 257 t adci calibration time after bit adc_globcfg.sucal is set t cal cc ?? 4352 cycle s total unadjusted error 6)5)13) tue cc -4 ? 4 14) lsb adc resolution= 12- bit adc = 0,1,2 -4 ? 4 14) lsb adc resolution= 12- bit 8) 9) adc3 and v ain v arefx - 0.15 v -14 ? 14 14) lsb adc resolution= 12- bit 8) 9) adc3 and v arefx - 0.15 v v ain < v arefx analog reference ground 2) v agndx sr v ssm - 0.05 ? v arefx - 1 v analog input voltage v ain sr v agndx ? v arefx v analog reference voltage 2) v arefx sr v agndx + 1 ? v ddm + 0.05 15) 16) v analog reference voltage range 6)5)2) v arefx - v agndx sr v ddm /2 ? v ddm + 0.05 v 1) the sampling capacity of the conversion c-network is pre-charged to v arefx /2 before the sampling moment. because of the parasitic elements the volt age measured at ainx can deviate from v arefx /2. 2) applies to ainx, when used as auxiliary reference input. table 23 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 129 v 1.1, 2014-05 the power-up calibration of the adc requires a maximum number of 4352 f adci cycles. 3) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead smaller capacitances are su ccessively switched to the reference voltage. 4) the sum of dnl/inl/gain/off errors does not exceed the related tue total unadjusted error. 5) if a reduced analog reference voltage between 1v and v ddm / 2 is used, then there are additional decrease in the adc speed and accuracy. 6) if the analog reference voltage range is below v ddm but still in the defined range of v ddm / 2 and v ddm is used, then the adc converter errors increase. if the reference voltage is reduced by the factor k (k<1), tue,dnl,inl,gain, and offset errors increase also by the factor 1/k. 7) if the analog reference voltage is > v ddm , then the adc converter errors increase. 8) for 10-bit conversions the error value must be multiplied with a factor 0.25. 9) for 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) for f adci between 18mhz and 20mhz the tue and gain e rror can increase beyond the given limits. for stc < 2 inl, dnl , and offset errors can also increase. 11) for a conversion time of 1 s a rms value of 85a result for i arefx. 12) the leakage current definition is a continuos function, as shown in fi gure adcx analoge input leakage. the numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 13) measured without noise. 14) for 10-bit conversion the tue is 2lsb; for 8-bit conversion the tue is 1lsb 15) a running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 16) if the reference voltage v arefx increase or the v ddm decrease, so that v aref = ( v ddm + 0.05v to v ddm + 0.07v), then the accuracy of the adc decrease by 4lsb12. table 24 conversion time (operating conditions apply) parameter symbol values unit note conversion time with post-calibration t c cc 2 t adc +(4+stc+n) t adci s n = 8, 10, 12 for n - bit conversion t adc =1/ f fpi t adci =1/ f adci conversion time without post-calibration 2 t adc +(2+stc+n) t adci
TC1798 electrical parametersdc parameters data sheet 130 v 1.1, 2014-05 figure 6 adcx input circuits reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx
TC1798 electrical parametersdc parameters data sheet 131 v 1.1, 2014-05 figure 7 adcx analog inputs leakage v in [v ddm %] 200na 500na 3% 100% 97% ioz1 100na -500na -100na v in [v ddm %] 300na 600na 3% 100% 97% ioz1 100na -600na -100na single adc input overlayed adc/fadc input
TC1798 electrical parametersdc parameters data sheet 132 v 1.1, 2014-05 5.2.3 fast analog to digital converter (fadc) fadc parameter are vaild for v dd / ddaf = 1.235 v to 1.365 v; v ddmf = 2.97 v to 3.6 v. table 25 fadc parameters parameter symbol values unit note / test condition min. typ. max. input current at vfaref i faref cc ?? 120 a input leakage current at vfaref 1) i foz2 cc -500 ? 500 na v faref v ddmf v; v faref 0v input leakage current at vfagnd i foz3 cc -500 ? 500 na dnl error ef dnl cc -1 ? 1lsb v in mode= differential; gain = 1 or 2 -2 ? 2lsb v in mode= differential; gain = 4 or 8 2) -1 ? 1lsb v in mode= single ended; gain = 1 or 2 -2 ? 2lsb v in mode= single ended; gain = 4 or 8 2) gradient error ef grad cc -5 ? 5% v in mode= differential ; gain 4 -5 ? 5% v in mode= single ended ; gain 4 -6 ? 6% v in mode= differential ; gain= 8 -6 ? 6% v in mode= single ended ; gain= 8
TC1798 electrical parametersdc parameters data sheet 133 v 1.1, 2014-05 inl error ef inl cc -4 ? 4lsb v in mode= differential -4 ? 4lsb v in mode= single ended offset error ef off cc -90 ? 90 mv v in mode= differential ; calibration= no -90 ? 90 mv v in mode= single ended ; calibration= no -20 ? 20 mv v in mode= differential ; calibration= ye s 3)4) -20 ? 20 mv v in mode= single ended ; calibration= ye s 3)4) error of commen mode voltage v faref /2 ef ref cc -60 ? 60 mv channel amplifier cutoff frequency f coff cc 2 ?? mhz converter clock f fadc sr 1 ? 100 mhz f fadc = f fpi conversion time t c cc ?? 21 1 / f fadc for 10-bit conversion input resistance of the analog voltage path (rn, rp) r fain cc 100 ? 200 koh m settling time of a channel amplifier after changing enn or enp t set cc ?? 5 s analog input voltage range v ainf sr v fagnd ? v ddmf v table 25 fadc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 134 v 1.1, 2014-05 the calibration procedure should run after each power-up, when all power supply voltages and the referenc e voltage have stabilized. analog reference ground v fagnd sr v ssaf - 0.05 ? v ssaf + 0.05 v analog reference voltage v faref sr 2.97 ? 3.63 5) 6) v 1) this value applies in power-down mode. 2) no missing codes. 3) calibration should be preformed at each power-up. in case of a continous operation, it should be performed minimium once per week. 4) the offser error voltage drifts over the whole temperature range maximum +-3lsb. 5) voltage overshoot to 4v is permissible, pr ovided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) a running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). table 25 fadc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 135 v 1.1, 2014-05 figure 8 fadc input circuits fadc_inprefdi ag = + - + - r n fainxn fainxp v fa g nd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fag nd v faref i faref
TC1798 electrical parametersdc parameters data sheet 136 v 1.1, 2014-05 5.2.4 oscillator pins note: it is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine th e optimal parameters for the oscillator operation. please refer to the limits specified by the crystal or ceramic resonator supplier. table 26 osc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input current at xtal1 i ix1 cc -25 ? 25 a v in < v ddosc3 ; v in >0 v input frequency f osc sr 4 ? 40 mhz direct input mode selected 8 ? 25 mhz external crystal mode selected oscillator start-up time 1) 1) t oscs is defined from the moment when v ddosc3 = 3.13v until the oscillations reach an amplitude at xtal1 of 0.3 * v ddosc3 . the external oscillator circuitry must be opti mized by the customer and checked for negative resistance as recommended and spec ified by crystral suppliers. t oscs cc ?? 10 ms input high voltage at xtal1 2) 2) if the xtal1 pin is driven by a crystal, reac hing a minimum amplitude (peak-to-peak) of 0.4 * v ddosc3 is necessary. v ihx sr 0.7 x v ddos c3 ? v ddos c3 + 0.5 v input low voltage at xtal1 v ilx sr -0.5 ? 0.3 x v ddos c3 v input hysteresis for xtal1 pad 3) 3) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. hysax cc ?? 200 mv
TC1798 electrical parametersdc parameters data sheet 137 v 1.1, 2014-05 5.2.5 temperature sensor the following formula calculates the temperature measured by the dts in [ o c] from the result bit field of the dtsstat register. (1) table 27 dts parameters parameter symbol values unit note / test condition min. typ. max. measurement time t m cc ?? 100 s temperature sensor range t sr sr -40 ? 150 c sensor accuracy (calibrated) t tsa cc -6 ? 6c start-up time after resets inactive t tsst sr ?? 20 s tj dtsstat result 596 ? 2 03 , ------------------------------------------------------------------ - =
TC1798 electrical parametersdc parameters data sheet 138 v 1.1, 2014-05 5.2.6 power supply current the total power supply current defined below consists of leakage and switching component. application relevant values are typically lower than those given in the following two tables and depend on the customer's system operatin g conditions (e.g. thermal connection or used application configurations). the operating conditions for the parameters in the following table are: vdd / v ddosc / v ddaf / v ddpf =1.365 v, vddp / v ddosc / v ddmf / v ddfl3 / v ddpf =3.47 v, fsri / cpu=300 mhz, fpcp=200 mh z, fsri=100 mhz, tj=150 oc the realisic power pattern defines the following conditions: ? tj=150 oc ? f sri = f cpu =300mhz ? f pcp =200mhz ? f fpi =100mhz ? v dd = v ddosc = v ddaf = v ddpf =1.326v ? v ddp = v ddosc3 = v ddfl3 v ddpf3 = v ddmf = 3.366 v ? v ddm =5.1v the max power pattern defines the following conditions: ? tj=150 oc ? f sri = f cpu =300mhz ? f pcp =200mhz ? f fpi =100mhz ? v dd = v ddosc = v ddaf = v ddpf =1.43v ? v ddp = v ddosc3 = v ddfl3 v ddpf3 = v ddmf =3.63v ? v ddm =5.5v table 28 power supply parameters parameter symbol values unit note / test condition min. typ. max. core active mode supply current 1)2) i dd cc ?? 890 3) ma power pattern= max; fcpu=300 mhz ?? 656 4) ma power pattern= realisti c; fcpu=300 mhz i dd current at porst low i dd_pors t cc ?? 298 ma tj=150 oc ?? 249 ma tj=140 oc
TC1798 electrical parametersdc parameters data sheet 139 v 1.1, 2014-05 e-ray pll core supply current i ddpf cc ?? 4ma oscillator core supply current i ddosc cc ?? 3ma fadc core supply current i ddaf cc ?? 26 ma sum of all 1.3 v supply currents i ddsum cc ?? 689 ma power pattern= realisti c; fcpu=300 mhz e-ray pll 3.3v supply i ddpf3 cc ?? 4ma oscillator power supply current, 3.3v i ddosc3 cc ?? 11 ma fadc analog supply current, 3.3v i ddmf cc ?? 15 ma i ddebu current at porst low i ddebu_p orst cc ?? 1ma i ddp current at porst low i ddp_por st cc ?? 7ma i ddp current no pad activity, lvds off 5) i ddp cc ?? i ddp_p orst + 25 ma including flash read current ?? i ddp_p orst + 55 ma including flash programming current 6) ?? i ddp_p orst + 40 7) ma including flash erase verify current 6) table 28 power supply parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 140 v 1.1, 2014-05 5.2.6.1 calculating the 1.3 v current consumption the current consumption of the 1.3 v rail compose out of two parts: ? static current consumption flash memory current 5) i ddfl3 cc ?? 98 ma flash read current ?? 29 ma flash programming current 6) ?? 98 ma flash erase current 6) current consumption of lvds pad pairs i lvds cc ?? 24 ma in total for all lvds pairs sum of all 3.3 v supply currents, no pad activity, lvds off i dd3sum cc ?? 161 8) ma including flash read current adc 5v power supply current i ddm cc ?? 8ma maximum power dissipation pd cc ?? 1808 mw power pattern= max; fcpu=300 mhz ?? 1547 mw power pattern= realisti c; fcpu=300 mhz 1) infineon power loop: cpu and pcp running, all peripherals active. the power consumption of each customer application will most probably be lower than this value, but must be evaluated seperately. 2) this current includes the e-ray module power consumption, including the pcp operation component. 3) the i dd decreases typically by 89ma if the f cpu decreases by 50mhz, at constant t j 4) the i dd decreases typically by 70ma if the f cpu decreases by 50mhz, at constant t j 5) for operations including the d-flash the required currents are always lower than the currents for non d-flash operation. 6) relevant for the power supply dimensi oning, not for thermal considerations. 7) in case of erase of program flash pfx, internal flash array loading effects may generate transient current spikes of up to 15 ma for maximum 5 ms per flash module. 8) for power supply dimensioning of v ddp 30 ma have to added for flash programming case. table 28 power supply parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersdc parameters data sheet 141 v 1.1, 2014-05 ? dynamic current consumption the static current consumption is related to the device temperature t j and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. these two parts needs to be added in order to get the rail current consumption. (2) (3) function 2 defines the typical static curren t consumption and function 3 defines the maximum static current consumption. both functions are valid for v dd =1.326v. for the dynamic current consumpti on using the application pattern and f sri =2* f pcp =3* f fpi the function 4 applies: (4) and this finally results in (5) i 0 375 ma c -------- - , e 0 02041 , t j c [] = i 0 18 77 ma c -------- - , e 0 01825 , t j c [] = i d y m 119 ma mhz ------------ - , f cpu mhz [] = i dd i 0 i dym + =
TC1798 electrical parametersac parameters data sheet 142 v 1.1, 2014-05 5.3 ac parameters that means, keeping the pads constantly at maximum strength. 5.3.1 testing waveforms figure 9 rise/fall time parameters figure 10 testing waveform, output delay figure 11 testing waveform, output high impedance 10 % 90% 10 % 90 % v ss v ddp t r rise_fall t f mct04881_a.vsd v dde / 2 test points v dde / 2 v ss v ddp mct04880_new v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
TC1798 electrical parametersac parameters data sheet 143 v 1.1, 2014-05 5.3.2 power sequencing figure 12 5 v / 3.3 v / 1.3 v power-up/down sequence the following list of rules applies to the power-up/down sequence: ? all ground pins v ss must be externally connected to one single star point in the system. regarding the dc current component, all ground pins are internally directly connected. ? at any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 v, or: vdd5 > vdd3.3 - 0.5 v; vdd5 > vdd1.3 - 0.5 v;vdd3.3 > vdd1.3 - 0.5 v, see figure 12 . ? the latch-up risk is minimized if the i/o currents are limited to: ? 20 ma for one pin group ? and 100 ma for the completed device i/os ? and additionally before power-up / after power-down: 1 ma for one pin in inactive mode (0 v on all power supplies) ? during power-up and power-down, the volt age difference between the power supply pins of the same voltage (3.3 v, 1.3 v, an d 5 v) with different names (for example vddp, vddfl3 ...), that are internally connected via diodes, must be lower than power-up 10.vsd 1.3v 3.3v 5v t v t -12% -12% porst 0.5v 0.5v 0.5v v ddp v aref power down power fail 3.47v 3.0v 1.235v 1.365v 4.75v 5.25v
TC1798 electrical parametersac parameters data sheet 144 v 1.1, 2014-05 100 mv. on the other hand, all power supply pins with the same name (for example all vddp), are internally directly connec ted. it is recommended that the power pins of the same voltage are driven by a single power supply. ? the porst signal may be deactivated after all vdd5, vdd3.3, vdd1.3, and varef power-supplies and the oscillator have reached stable operation, within the normal operating conditions. ? at normal power down the porst signal should be activated within the normal operating range, and then the power supp lies may be switched off. care must be taken that all flash write or dele te sequences have been completed. ? at power fail the porst signal must be ac tivated at latest when any 3.3 v or 1.3 v power supply voltage falls 12% below the no minal level. if, under these conditions, the porst is activated during a flash writ e, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. in order to ensure clean power-down behavior, t he porst signal should be activated as close as possible to the normal operating voltage range. ? in case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rules number 2 and 4. ? although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. ? additionally, regarding the adc reference voltage varef: ? varef must power-up at the same time or later then vddm, and ? varef must power-down either earlier or at latest to satisfy the condition varef < vddm + 0.5 v. this is required in order to prevent discharge of varef filter capacitance through the esd diode s through the vddm power supply. in case of discharging the reference ca pacitance through the esd diodes, the current must be lower than 5 ma.
TC1798 electrical parametersac parameters data sheet 145 v 1.1, 2014-05 5.3.3 power, pad and reset timing table 29 reset timings parameters parameter symbol values unit note / test condition min. typ. max. application reset boot time 1)2) 1) the duration of the boot time is defined between the ri sing edge of the internal application reset and the clock cycle when the first user instruction has entered the cpu pipeline and its processing starts. 2) the given time includes the time of the internal reset extension for a configured value of scu_rstcntcon.relsa = 0x05be. t b cc ?? 880 s f cpu =300mhz power on reset boot time 3)4) 3) the duration of the boot time is defined between the rising edge of the porst and the clock cycle when the first user instruction has entered the cpu pipeline and its processing starts. t bp cc ?? 2.5 ms hwcfg pins hold time from esr0 rising edge t hdh sr 16 / f fpi ?? ns hwcfg pins setup time to esr0 rising edge t hds sr 0 ?? ns ports inactive after esr0 reset active t pi cc ?? 8/ f fpi ns ports inactive after porst reset active 5) t pip cc ?? 150 ns minimum porst active time after power supplies are stable at operating levels t poa sr 10 ?? ms testmode /trst hold time from porst rising edge t poh sr 100 ?? ns porst rise time t por sr ?? 50 ms testmode /trst setup time to porst rising edge t pos sr 0 ?? ns application reset inactive after porst deassertion t por_app sr ?? 40 6) s
TC1798 electrical parametersac parameters data sheet 146 v 1.1, 2014-05 figure 13 power, pad and reset timing 4) the given time includes the internal reset extension time for the system and application reset which is visible through esr0. 5) this parameter includes the delay of the analog spike filter in the porst pad. 6) application reset is assumed not to be extended from external, otherwise the time extends by the time the application reset is extended. reset_beh2 as programmed vddp pads pad- state undefined vdd v d d ppa v ddppa t hd t poa t poa trst testmode esr0 porst t poh hwcfg t hdh t pip t pi tri -state or pull device active t hd t poh t hdh t pip t pi t pip t pi t pi t hdh t pi v ddp -12% v dd -12%
TC1798 electrical parametersac parameters data sheet 147 v 1.1, 2014-05 5.3.4 phase locked loop (pll) phase locked loop operation when pll operation is enabled and configured, the pll clock f vco (and with it the sri- bus clock f sri ) is constantly adjusted to the sele cted frequency. the pll is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter t hat is limited. this means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. this is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. for all slower operations and lo nger periods (e.g. pulse train generation or measurement, lower baudrates, et c.) the deviation caused by the pll jitter is negligible. table 30 pll_sysclk parameters parameter symbol values unit note / test condition min. typ. max. accumulated jitter d p cc -7 ? 7ns modulation frequency f mod sr 50 ? 200 khz pll base frequency f pllbase cc 50 200 320 mhz vco input frequency f ref cc 8 ? 16 mhz vco frequency range f vco cc 400 ? 720 mhz with inactive modulation 400 ? 600 mhz with active modulation modulation jitter j mod cc ?? 2.5 ns total long term jitter j tot cc ?? 9.5 ns modulation amplitude ma sr 0 ? 2.5 % pll lock-in time t l cc 14 ? 200 sn>32 14 ? 400 sn 32 system frequency deviation f sysd cc ?? 0.01 % with active modulation
TC1798 electrical parametersac parameters data sheet 148 v 1.1, 2014-05 two formulas are defined for the (absolute) approximate maximum value of jitter d m in [ns] dependent on the k2 - factor, the sri clock frequency f sri in [mhz], and the number m of consecutive f sri clock periods. (6) (7) with rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the k2-factor of the pll. beyond this value of m the maximum accumulated jitter remains at a constant valu e. further, a lower sri-bus clock frequency f sri results in a higher abso lute maximum jitter value. note: the specified pll jitter values are va lid if the capacitive load per pin does not exceed c l = 20 pf with the maximum driver and sharp edge. note: the maximum peak-to-peak noise on the pad supply voltage, measured between v ddosc3 and v ssosc , is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. the maximum peak-to peak noise on the pad supply voltage, measured between v ddosc and v ssosc , is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. these conditions can be achieved by appr opriate blocking of the supply voltage as near as possible to the supply pins and using pcb supply and ground planes. oscillator watchdog (osc_wdt) the expected input frequency is selected via the bit field scu_osccon.oscval. the osc_wdt checks for too low frequencies and for too high frequencies. the frequency that is monitored is f oscref which is derived for f osc . (8) the divider value scu_osccon.oscval has to be selected in a way that f oscref is 2.5 mhz. for k2 100 () and m f sri mhz [] () 2 ? () d mns [] 740 k2 f sri mhz [] ----------------------------------------- - 5 + ?? ?? 1001 , k2 ? () m1 ? () 05 , f sri mhz [] 1 ? ---------------------------------------------------------------- 001 , k2 + ?? ?? = else d mns [] 740 k2 f sri mhz [] ----------------------------------------- - 5 + = f oscref f osc oscval 1 + ---------------------------------- - =
TC1798 electrical parametersac parameters data sheet 149 v 1.1, 2014-05 note: f oscref has to be within the range of 2 mhz to 3 mhz and should be as close as possible to 2.5 mhz. the monitored frequency is too low if it is below 1.25 mhz and too high if it is above 7.5 mhz. this leads to the following two conditions: ?too low: f osc <1.25mhz (scu_osccon.oscval+1) ? too high: f osc >7.5mhz (scu_osccon.oscval+1) note: the accuracy is 30% for these boundaries. frequency modulation frequency modulation defines a slow and predi ctable variation of the clock speed. the modulation configuration itself is contro lled via register scu_pllcon2 where the two bit fields define the modulation properties. (9) (10) f mod f osc p -------------- modfreq 31 32 , modamp ---------------------------------------------------- = ma modamp n161 ---------------------------- =
TC1798 electrical parametersac parameters data sheet 150 v 1.1, 2014-05 5.3.5 eray phase locked loop (eray_pll) note: the specified pll jitter values are va lid if the capacitive load per pin does not exceed c l = 20 pf with the maximum driver and sharp edge. note: the maximum peak-to-peak noise on the pad supply voltage, measured between v ddpf3 and v sspf , is limited to a peak-to-peak voltage of v pp =100mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. these conditions can be achieved by appr opriate blocking of the supply voltage as near as possible to the supply pins and using pcb supply and ground planes. table 31 pll_eray parameters parameter symbol values unit note / test condition min. typ. max. accumulated jitter at sysclk pin d pp cc -0.8 ? 0.8 ns accumulated_jitter d p cc -0.5 ? 0.5 ns pll base frequency of the eray pll f pllbase_ eray cc 50 250 360 mhz vco input frequency of the eray pll f ref cc 20 ? 40 mhz vco frequency range of the eray pll f vco_era y cc 450 ? 500 mhz pll lock-in time t l cc 5.6 ? 200 s
TC1798 electrical parametersac parameters data sheet 151 v 1.1, 2014-05 5.3.6 jtag interface timing the following parameters are applicable for communication through the jtag debug interface. the jtag module is fu lly compliant with ieee1149.1-2000. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. table 32 jtag interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 25 ? ? ns ? tck high time t 2 sr 10 ? ? ns ? tck low time t 3 sr 10 ? ? ns ? tck clock rise time t 4 sr??4ns? tck clock fall time t 5 sr??4ns? tdi/tms setup to tck rising edge t 6 sr 6 ? ? ns ? tdi/tms hold after tck rising edge t 7 sr6??ns? tdo valid after tck falling edge 1) (propagation delay) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc??13nsc l =50pf t 8 cc3??nsc l =20pf tdo hold after tck falling edge 1) t 18 cc2??ns tdo high imped. to valid from tck falling edge 1)2) 2) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc??14nsc l =50pf tdo valid to high imped. from tck falling edge 1) t 10 cc ? ? 13.5 ns c l =50pf
TC1798 electrical parametersac parameters data sheet 152 v 1.1, 2014-05 figure 14 test clock timing (tck) figure 15 jtag timing mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18
TC1798 electrical parametersac parameters data sheet 153 v 1.1, 2014-05 5.3.7 dap interface timing the following parameters are applicable for communication through the dap debug interface. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. figure 16 test clock timing (dap0) table 33 dap parameters parameter symbol values unit note / test condition min. typ. max. dap0 clock period 1) 1) see the dap chapter for clock rate restrictions in the active:idle protocol state. t tck sr 12.5 ?? ns dap0 high time t 12 sr 4 ?? ns dap0 low time 1) t 13 sr 4 ?? ns dap0 clock rise time t 14 sr ?? 2ns dap0 clock fall time t 15 sr ?? 2ns dap1 setup to dap0 rising edge t 16 sr 6.0 ?? ns dap1 hold after dap0 rising edge t 17 sr 6.0 ?? ns dap1 valid per dap0 clock period 2) 2) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 cc 8 ?? ns c l =20pf; f =80mhz 10 ?? ns c l =50pf; f =40mhz mc_dap0 0.9 v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14
TC1798 electrical parametersac parameters data sheet 154 v 1.1, 2014-05 figure 17 dap timing host to device figure 18 dap timing device to host 5.3.8 micro link interface (mli) timing t 16 t 17 dap0 dap1 mc_ dap1_rx dap1 mc_ dap1_tx t 11 t 19
TC1798 electrical parametersac parameters data sheet 155 v 1.1, 2014-05 figure 19 mli interface timing note: the generation of rreadyx is in the input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. the mli parameters are vaild for c l = 50 pf and strong driver medium edge. t 27 t 25 t 26 t 16 t 17 t 15 t 15 mli_tmg_2.vsd tdatax tvalidx tclkx rdatax rvalidx rclkx treadyx rreadyx t 10 t 13 t 11 t 12 t 14 t 20 t 27 mli transmitter timing mli receiver timing t 23 t 21 t 22 t 24
TC1798 electrical parametersac parameters data sheet 156 v 1.1, 2014-05 table 34 mli receiver parameter symbol values unit note / test condition min. typ. max. rclk clock period t 20 sr 1 / f fpi ?? ns rclk high time 1)2) 1) the following formula is valid: t21 + t22 = t20. 2) min and max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters. t 21 sr ? 0.5 x t 20 ? ns rclk low time 1)2) t 22 sr ? 0.5 x t 20 ? ns rclk rise time 3) 3) the rclk max. input rise/fall times are best case parameters for fsys = 90 mhz. for reduction of emi, slower input signal rise/fall times can be used for longer rclk clock periods. t 23 sr ?? 4ns rclk fall time 3) t 24 sr ?? 4ns rdata/rvalid setup time before rclk falling edge t 25 sr 4.2 ?? ns rdata/rvalid hold time after rclk falling edge t 26 sr 2.2 ?? ns rready output delay time t 27 sr 0 ? 16 ns table 35 mli transmitter parameter symbol values unit note / test condition min. typ. max. tclk clock period t 10 cc 2 x 1 / f fpi ?? ns tclk high time 1)2) t 11 cc 0.45 x t 10 0.5 x t 10 0.55 x t 10 ns tclk low time 1)2) t 12 cc 0.45 x t 10 0.5 x t 10 0.55 x t 10 ns tclk rise time t 13 cc ?? 0.3 x t 10 3) ns tclk fall time t 14 cc ?? 0.3 x t 10 3) ns
TC1798 electrical parametersac parameters data sheet 157 v 1.1, 2014-05 5.3.9 micro second channel (msc) interface timing the msc parameters are vaild for c l =50pf. tdata/tvalid output delay time t 15 cc -3 ? 4.4 ns tready setup time before tclk rising edge t 16 sr 18 ?? ns tready hold time after tclk rising edge t 17 sr -2 ?? ns 1) the following formula is valid: t11 + t12 = t10. 2) the min./max. tclk low/high times t11/t12 include the pll jitter of fsys. fractional divider settings must be regarded additionally to t11 / t12. 3) for high-speed mli interface, strong driver sharp or medium edge selection (class a2 pad) is recommended for tclk. table 36 msc parameters parameter symbol values unit note / test condition min. typ. max. fclp clock period 1)2) t 40 cc 2 x t msc 3) ?? ns sop 4) /enx outputs delay from fclp 4) rising edge t 45 cc -2 ? 5 ns enx with strong driver and sharp (minus ) edge -2 ? 10 ns enx with strong driver and medium (minus) edge 0 ? 21 ns enx with strong driver and soft edge sdi bit time t 46 cc 8 x t msc ?? ns table 35 mli transmitter (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersac parameters data sheet 158 v 1.1, 2014-05 figure 20 msc interface timing note: the data at sop should be sampled with the falling edge of fclp in the target device. sdi rise time t 48 sr ?? 200 ns sdi fall time t 49 sr ?? 200 ns 1) fclp signal rise/fall times are only defined by the pad rise/fall times. 2) fclp signal high and low can be minimum 1xt msc 3) tmsc = tsys = 1 / fsys. 4) sop / fclp either propagated by lvds or by cmos strong driver and non soft edge. table 36 msc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max. msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi
TC1798 electrical parametersac parameters data sheet 159 v 1.1, 2014-05 5.3.10 ssc master/slave mode timing the ssc parameters are vaild for c l = 50 pf and strong driver medium edge. table 37 ssc parameters parameter symbol values unit note / test condition min. typ. max. sclk clock period 1)2)3) 1) sclk signal rise/fall times are the same as the rise/fall times of the pad. 2) sclk signal high and low times can be minimum 1xtssc. 3) tsscmin = tsys = 1/fsys. t 50 cc 2 x 1 / f fpi ?? ns mtsr/slsox delay form sclk rising edge t 51 cc 0 ? 8ns mrst setup to sclk latching edge 3) t 52 sr 16.5 ?? ns mrst hold from sclk latching edge 3) t 53 sr 0 ?? ns sclk input clock period 1)3) t 54 sr 4 x 1 / f fpi ?? ns sclk input clock duty cycle t 55 _ t 54 sr 45 ? 55 % mtsr setup to sclk latching edge 3)4) 4) fractional divider switched off, ssc internal baud rate generation used. t 56 sr 1 / f fpi ?? ns mtsr hold from sclk latching edge t 57 sr 1 / f fpi + 5 ?? ns slsi setup to first sclk latching edge t 58 sr 1 / f fpi + 5 ?? ns slsi hold from last sclk latching edge 5) t 59 sr 7 ?? ns mrst delay from sclk shift edge t 60 cc 0 ? 16.5 ns slsi to valid data on mrst t 61 cc ?? 16.5 ns
TC1798 electrical parametersac parameters data sheet 160 v 1.1, 2014-05 figure 21 ssc master mode timing 5) for con.ph=1 slave select must not be removed before the following shifting edge. this mean, that what ever is configured (shifting / latching first), slsi must not be de-actived before the last trailing edge from the pair of shifting / latching edges. ssc_tmgmm sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slson 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slson is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50
TC1798 electrical parametersac parameters data sheet 161 v 1.1, 2014-05 figure 22 ssc slave mode timing ssc_tmgsm sclk 1) t 55 mtsr 1) t 57 data valid t 56 slsi t 58 1) this timing is based on the following setup: con.ph = con.po = 0. t 54 t 55 t 59 last latching sclk edge first latching sclk edge t 57 data valid t 56 mrst 1) t 60 first shift sclk edge t 60 t 61
TC1798 electrical parametersac parameters data sheet 162 v 1.1, 2014-05 5.3.11 eray interface timing the timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with c l = 25 pf. the eray interface is only availa ble for the sak-tc 1798f-512f300ep / sak- TC1798f-512f300el / sak-TC1798s-512f300ep. table 38 eray parameters parameter symbol values unit note / test condition min. typ. max. time span from last bss to fes without the influence of quartz tolerancies (d10bit_tx) 1) 1) this includes the pll_eray accumulated jitter. t 60 cc 997.75 ? 1002.2 5 ns txd data valid from fsample flip flop txd_reg txda, txdb (dtxasym) 2)3) 2) refers to delays caused by the asymmetries of the output drivers of the digital logic and the gpio pad drivers. quarz tolerance and pll_eray accumulated jitter are not included. 3) e-ray txd output drivers have an asymmetry of rising and falling edges of | t fa2 - t ra2 | 1 ns. t 61 - t 62 cc ?? 1.5 ns asymmetrical delay of rising and falling edge (txda, txdb) time span between last bss and fes without influence of quartz tolerancies (d10bit_rx) 1)4)5) 4) limits of 966ns and 1046.1ns correspond to (30%, 70%) * v ddp flexray standard input thresholds. for input thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied. t 63 sr 966 ? 1046.1 ns rxd capture by fsample (rxda/rxdb sampling flip-flop) (drxasym) 6) t 64 - t 65 cc ?? 3.0 ns asymmetrical delay of rising and falling edge (rxda, rxdb) txd data delay from sampling flip-flop dtxdly cc ?? 10.0 ns px_pdr.pdy = 000 b ?? 15.0 ns px_pdr.pdy = 001 b rxd capture delay by sampling flip-flop drxdly cc ?? 10.0 ns
TC1798 electrical parametersac parameters data sheet 163 v 1.1, 2014-05 figure 23 eray timing 5) valid for output slopes of the bus driver of drxslope 5ns, 20% * v ddp to 80% * v ddp , according to the flexray electrical physical layer specification v2.1b. for a2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns t fa2 - t ra2 1.3ns. 6) valid for output slopes of the bus driver of drxslope 5ns, 20% * v ddp to 80% * v ddp , according to the flexray electrical physical layer specification v2.1b. for a2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns t fa2 - t ra2 1.3ns. txd t 60 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) eray_timing rxd t 63 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) 0.9 v dd 0.1 v dd txd t 61 t 62 t sample 0.7 v dd 0.3 v dd rxd t 64 t 65 t sample
TC1798 electrical parametersac parameters data sheet 164 v 1.1, 2014-05 5.3.12 ebu timings 5.3.12.1 bfclko output clock timing v ss = 0 v; v dd = 1.3 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%,; c l = 35 pf figure 24 bfclko ou tput clock timing 5.3.12.2 ebu asynchronous timings v ss = 0 v; v dd = 1.3 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; c l = 35 pf for address/data; c l = 40pf for the control lines. for each timing, the accumulated pll jitter of the programed duration in number of clock periods must be added separately. operating conditions apply and c l = 35 pf. table 39 bfclk0 output clock timing parameters 1) 1) not subject to production test, ve rified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. bfclko clock period t bfclko cc 13.33 2) 2) the pll jitter characteristics add to this value ac cording to the application settings. see the pll jitter parameters. ?? ns? bfclko high time t 5 cc 3 ? ? ns ? bfclko low time t 6 cc 3 ? ? ns ? bfclko rise time t 7 cc ? ? 3 ns ? bfclko fall time t 8cc ??3ns? bfclko duty cycle t 5 /( t 5 + t 6 ) 3) 3) the pll jitter is not included in this para meter. if the bfclko frequency is equal to f cpu , the k divider has to be regarded. dc 35 50 55 % ? 0.9 v dd mct04883_mod 0.5 v ddp05 bfclko t bfclko t 5 t 6 0.1 v dd t 8 t 7
TC1798 electrical parametersac parameters data sheet 165 v 1.1, 2014-05 table 40 ebu common asynchronous timings parameter symbol values unit note / test condition min. typ. max. pulse wdih deviation from the ideal programmed width due to b pad asymmetry, rise delay - fall delay 1) 1) not subject to production test, ve rified by design/characterization. t a cc -0.8 ? 0.8 ns edge= medium -0.8 ? 0.8 ns edge= sharp ad(31:0) output delay to adv# rising edge, multiplexed read / write 1) t 13 cc -5.5 ? 2ns ad(31:0) output delay to adv# rising edge, multiplexed read / write 1) t 14 cc -5.5 ? 2ns address valid to cs falling edge (deviation from programmed value) 1) t 15 cc -2 ? 2ns address valid to adv falling edge (deviation from programmed value) 1) t 16 cc -2 ? 2ns adv falling edge -> csfalling edge (deviation from programmed value) 1) t 17 cc -2 ? 2ns
TC1798 electrical parametersac parameters data sheet 166 v 1.1, 2014-05 table 41 ebu asynchronous read timings parameter symbol values unit note / test condition min. typ. max. a(23:0) output delay to rd rising edge, deviation from the ideal programmed value 1) t 0 cc -2.5 ? 2.5 ns a(23:0) output delay to rd rising edge, deviation from the ideal programmed value 1) t 1 cc -2.5 ? 2.5 ns cs rising edge to rd rising edge, deviation from the ideal programmed value 1) t 2 cc -2 ? 2.5 ns adv rising edge to rd rising edge, deviation from the ideal programmed value 1) t 3 cc -1.5 ? 4.5 ns bc rising edge to rd rising edge, deviation from the ideal programmed value 1) t 4 cc -2.5 ? 2.5 ns wait input setup to rd rising edge, deviation from the ideal programmed value 1) t 5 sr 12 ?? ns wait input hold to rd rising edge, deviation from the ideal programmed value 1) t 6 sr 0 ?? ns data input setup to rd rising edge, deviation from the ideal programmed value 1) t 7 sr 12 ?? ns
TC1798 electrical parametersac parameters data sheet 167 v 1.1, 2014-05 data input hold to rd rising edge, deviation from the ideal programmed value 1) t 8 sr -2 ?? ns mr / w output delay to rd# rising edge, deviation from the ideal programmed value 1) t 9 cc -2.5 ? 1.5 ns data input hold from cs rising edge 1) t 18 cc -2 ?? ns data input setup to cs rising edge 1) t 19 cc 12 ?? ns 1) not subject to production test, ve rified by design/characterization. table 41 ebu asynchronous read timings (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersac parameters data sheet 168 v 1.1, 2014-05 figure 25 multiplexed read access new_muxrd_async_10.vsd cs[3:0] cscomb adv rd mr/w ad[31:0] data in bc[3:0] wait a[23:0] valid address next addr. address out t 2 t a t a t a t a t 4 t 5 t 6 t a t 13 t 14 t 7 t 8 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 1 t 0 pv + pv + pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) command delay phase cmddelay 0...7
TC1798 electrical parametersac parameters data sheet 169 v 1.1, 2014-05 figure 26 demultiplexed read access new_demuxrd_async_10.vsd cs[3:0] cscomb adv rd mr/w ad[31:0] data in bc[3:0] wait a[23:0] valid address next addr. t 2 t a t a t a t a t 4 t 5 t 6 t a t 7 t 8 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 1 t 0 pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) new addr. phase
TC1798 electrical parametersac parameters data sheet 170 v 1.1, 2014-05 table 42 ebu asynchnronous write timings parameter symbol values unit note / test condition min. typ. max. a(23:0) output delay to wr rising edge, deviation from the ideal programmed value 1) t 30 cc -2.5 ? 2.5 ns a(23:0) output delay to wr rising edge, deviation from the ideal programmed value 1) t 31 cc -2.5 ? 2.5 ns cs rising edge to wr rising edge, deviation from the ideal programmed value 1) t 32 cc -2 ? 2ns adv rising edge to wr rising edge, deviation from the ideal programmed value 1) t 33 cc -2.5 ? 2ns bc rising edge to wr rising edge, deviation from the ideal programmed value 1) t 34 cc -2.5 ? 2ns wait input setup to wr rising edge, deviation from the ideal programmed value 1) t 35 sr 12 ?? ns wait input hold to wr rising edge, deviation from the ideal programmed value 1) t 36 sr 0 ?? ns data output delay to wr falling edge, deviation from the ideal programmed value 1) t 37 cc -5.5 ? 2ns
TC1798 electrical parametersac parameters data sheet 171 v 1.1, 2014-05 5.3.12.3 ebu burst mode access timing v ss = 0 v; v dd = 1.3 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; c l = 35 pf; data output delay to wr rising edge, deviation from the ideal programmed value 1) t 38 cc -5.5 ? 2ns mr / w output delay to wr rising edge, deviation from the ideal programmed value 1) t 39 cc -2.5 ? 1.5 ns 1) not subject to production test, ve rified by design/characterization. table 43 ebu burst read timings parameter symbol values unit note / test condition min. typ. max. output delay from bfclko rising edge 1) t 10 cc -2 ? 2ns rd and rd/wr active/inactive after bfclko active edge 1)2) t 12 cc -2 ? 2ns csx output delay from bfclko active edge 1)2) t 21 cc -2.5 ? 1.5 ns adv active/inactive after bfclko active edge 1)3) t 22 cc -2 ? 2ns baa active/inactive after bfclko active edge 1)3) t 22a cc -2.5 ? 1.5 ns data setup to bfclki rising edge 1) t 23 sr 3 ?? ns data hold from bfclki rising edge 1) t 24 sr 0 ?? ns table 42 ebu asynchnronous write timings (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersac parameters data sheet 172 v 1.1, 2014-05 wait setup (low or high) to bfclki rising edge 1) t 25 sr 3 ?? ns wait hold (low or high) from bfclki rising edge 1) t 26 sr 0 ?? ns 1) not subject to production test, ve rified by design/characterization. 2) an active edge can be rising or falling edge, depending on the settings of bits bfcon.ebse / ecse and clock divider ratio. negative minimum values for these para meters mean that the last data read during a burst may be corrupted. however, with clock feedback enabled, th is value is oversampling not required for the lmb transaction and will be discarded. if the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as at asynchronous access. so t14, t15, t16, t17, t18 and t19 from the asynchronous timings apply. 3) for busconx.ebse=1b and busapx.exlclk=00b, adv will change normally on the clock edge so this parameter is used directly. for busconx.ebse=1b and other values of busapx.extclk, adv and baa add the high pulse width of ebuclk to this parameter. for busconx.ebse=0b and busapx.extclk=00b add the high pulse width of ebuclk to this parameter. for busconx.ebse=0b and busapx.extclk=11b add two ebuclk periodsto this parameter to get the hold time from bfclko rising edge to the adv. for busconx.ebse=0b and busapx.extclk=01b or 10b add 1 ebuclk period. please note that the high pulse width of ebuclk is defined by the high pulse width of fvco of the used pll. table 43 ebu burst read timings (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersac parameters data sheet 173 v 1.1, 2014-05 figure 27 ebu burst mode read / write access timing data (addr+4) burstrdwr_4.vsd t 10 bfclki bfclko a[23:0] t 22 adv t 21 address phase(s) command phase(s) burst phase(s) recovery phase(s) next addr. phase(s) t 22 t 21 t 21 burst start address next addr. rd rd/wr d[31:0] (32-bit) wait t 12 t 12 data (addr+0) t 24 baa d[15:0] (16-bit) t 22a burst phase(s) data (addr+2) data (addr+0) t 22a t 10 t 22 t 23 t 24 t 23 1) t 26 t 25 output delays are always referenced to bclko. the reference clock for input characteristics depends on bit ebu_bfcon.fdbken. ebu_bfcon.fdbken = 0: bfclko is the input reference clock. ebu_bfcon.fdbken = 1: bfclki is the input reference clock (ebu clock feedback enabled). 1) cs[3:0] cscomb
TC1798 electrical parametersac parameters data sheet 174 v 1.1, 2014-05 5.3.12.4 ebu arbitration signal timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a =-40 c to +125 c; c l = 35 pf; figure 28 ebu arbitration signal timing table 44 ebu ebu arbitration timings parameter symbol values unit note / test condition min. typ. max. output delay from bfclko rising edge 1) 1) not subject to production test, ve rified by design/characterization. t 27 cc ?? 3ns data setup to bfclko falling edge 1) t 28 sr 8 ?? ns data hold from bfclko falling edge 1) t 29 sr 2 ?? ns ebuarb_1 bfclko hlda output breq output t 27 t 27 t 27 t 27 t 29 t 28 t 29 t 28 bfclko hold input hlda input
TC1798 electrical parametersac parameters data sheet 175 v 1.1, 2014-05 5.3.12.5 ebu ddr timing parameters parameters applicable when using the ebu to access ddr memories table 45 is valid under the following conditions: c l 20 pf; v ddebu = 1.8 5% v table 45 ebu ddr timings parameter symbol values unit note / test condition min. typ. max. ddr clock signal fall time t cf cc ?? 3.3 ns ddr clock signal high time t ch cc 29 ? 71 % ddr clock signal period 1) t ck cc 24.0 ?? ns skew between clock rising transition and dqs rising edge or clock falling transition and dqs falling edge 2) t ckdqs cc -1.2 ? 1.2 ns ddr clock signal low time t cl cc 47 ? 53 % ddr clock signal rise time t cr cc ?? 3.3 ns maximum time from falling clock edge until ddr control signal is valid 3) t cva cc ?? 5ns maximum time before falling clock edge that ddr control signal can become invalid 3) t cvb cc ?? 5ns dll delay time for duty cycle correction when locked t dcc cc t ebu / 2 - 0.3 ? t ebu / 2 + 0.3 ns byte lane x signals valid value hold time (dq & dm) after dqsx edge 4) t dh1 cc -1.6 5) ?? ns dll delay time for for dq and dm when locked with dllcon.wr_adj=0d t dll cc t ebu / 4 - 0.2 ? t ebu / 4 + 0.2 ns
TC1798 electrical parametersac parameters data sheet 176 v 1.1, 2014-05 dll delay time for dqs when locked with dllcon.rd_adj=0d t dllr cc t ebu / 4 - 0.15 ? t ebu / 4 + 0.15 ns dq and dqs all signals hold time after ddrclk0 edge, ddrclk0 controlled read t dqckh cc 1.0 ?? ns dq and dqs all signal valid to ddrclk0 edge, ddrclk0 controlled read t dqcks cc 1.2 ?? ns dqsx edge to byte lane x signals valid (dq & dm) 4) t ds1 cc ?? 1.0 ns maximum peak to peak jitter of the ddr clock output t pkpk cc ?? 0ns dq byte lane hold time after dqsx edge, minimum hold time to guarantee read data capture, dll controlled read t qh sr 1.0 ?? ns dq byte lane valid to dqsx edge minimum setup time to guarantee read data capture, dll controlled read 6)4) t qs sr 1.0 ?? ns 1) this is a configuration constraint and not a design limit. application code must not configure the ebu to generate a ddr clock with a period of less than 12ns. 2) to allow for the differential clock trigger point being different from the trigger point on each of the individual signals, this parameter will be characterised separately for each of the clock signals oclko, ddrclko and ddrclko with a limit of 1 ns 3) to allow for the differential clock trigger point being different from the trigger point on each of the individual signals, this parameter will be characterised separately for each of the clock signals ddrclko (sdclko) and ddrclko with a limit of 2.4 ns 4) x = 0 to 3 5) i.e. signal can become invalid at most tdh1 before the clock edge 6) falling or rising edge table 45 ebu ddr timings (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersac parameters data sheet 177 v 1.1, 2014-05 timing for ebu ddr clock outputs the ebu provides three possible ddr clock outputs depending on the type of device being accessed. these are ? differential clock for accessing devi ces using a ddram type protocol on the ddrclko and ddrclko pins. ? differential clock for access ing devices using a burst flash type protocol on the bfclko and ddrclko pins. ? a single-ended clock on oclko (mr/w ) for interfacing to onfi 2 compliant devices. all these clocks operate with identical timing parameters and have a restricted load limit of 10pf for ddr operation. the rising edge on the differential clocks is defined as when a rising edge on ddrclko or bfclko transitions past a falling edge on ddrclko . timings apply at vdd ebu = 1.8 volts figure 29 timing waveform for ddr clock signals timing for ebu ddr control outputs the ebu control state machine will ensure that commands and signal transitions are generated in the correct clock cycle to meet device requirements. this section also applies when accessing sdram devices. the ebu will generate address (a [15:0]) and control (cke, ras , cas , wr ) outputs on the falling edge of the ddr clock to allow nominally symmetric setup and hold margins around the rising edge of the clock. for sdram devices, the same address and control signals are required but, in addition, the wr ite data (ad[31:0]) and dqm signals (bc[3:0] ) are required to meet the same timing requirements. as these parameters apply to sdram as well as ddr devices, the load limit should be taken to be 40pf. 0.9 vdd ebu 0.5 vdd ebu t ck t ch t cl 0.1 vdd ebu t cf t cr
TC1798 electrical parametersac parameters data sheet 178 v 1.1, 2014-05 figure 30 ddr command and address timing using the ddrncon.amode field, the timing of the address can be changed so that the address changes on the rising clock edge and is held for two clock cycles. this allows a nominal setup and hold margin of a full cl ock cycle. this mode is not compatible with burst length of two as commands needing a valid address output can then be generated in consecutive clock cycles. timing of ddr write data the ebu will generate the dq (write data) dm and dqs signals in two different modes depending on the ratio of the internal to external clocks. if the ratio is 1:1, then the clock used to generate the dq and dm outputs must be shifted by the dll by 25% of the external clock period (nominal value). if the ratio is 1:2 or 1:4, then the dq and dm signals will be generated using edges of the internal clock and the dll must not be used to further adjust the edge timing. a ratio of 1:3 is not supported. in all cases, the edges of the dqs signals ar e nominally aligned to the clock output and the dqs waveform is in phase with, and the same frequency as, the memory device clock input. valid ddrclko ddrclko don't care t0 t1 t2 t cva cke command addr t cvb t cva t cva t cvb nop valid t cva t cvb
TC1798 electrical parametersac parameters data sheet 179 v 1.1, 2014-05 the ebu is characterised with the dll inacti ve, so the timing parameters are specified for this case. for the 1:1 operating mode, the dll shift time and its error margin has to be added where appropriate. fo r the 1:2 or 1:4 cases, the signals will be generated by the appropriate clock edge so will be delayed by the correct number of ebu clock periods (t ebu ). in this case the clock jitter will need to be subtracted from the available setup and hold margins. figure 31 signal relati onship for ddr writes 1:1 internal to external clock ratio if the external bus clock is running at the same frequency as the internal clock, then the dll is used to generate intermediate clock edg es at the intervals necessary to correctly position the transitions on dq and dm using the defined parameters. in the case where the ddr memory clock is the same frequency as the internal ebu clock and the dll is enabled but the dll?s internal duty cycle correction is not in use: ?t dh for the memory will be t ck /2+t dh1 -tdll ?t ds for the memory will be t ck /2-t ds1 -tdll-t jit 1) if the duty cycle correction is in use (dllcon.dcc_en=1 b ), then the equation for setup becomes: 1) t jit is the pk-pk clock jitter of the ebu internal clock dm[3:0] ddrclko dqs[3:0] t ck (nom) dq[31:0] don't care data valid transitioning data t0 write command issued at t0 ddrclko dq and dm signals shown with dll disabled. with dll enabled, dq and dqm will be delayed by 0.25*t ck (nominal) t ckdqs t ckdqs t dh1 t ds1
TC1798 electrical parametersac parameters data sheet 180 v 1.1, 2014-05 ?t ds for the memory will be t ck /2-t ds1 -tdll-(2*t jit ) ?t dh for the memory will be t ck /2+t dh1 -tdll 1:2 internal to external clock ratio if the external bus clock is running at half the internal clock frequ ency, then the negative phase clock is used to generate intermediate clock edges at the intervals necessary to correctly position the transitions on dq and dm the negative phase clock is generated either by: ? if the ebu internal clock is a pulse swa llowed version of the system clock then the negative phase clock is generated by swa llowing alternate pulses. so if the main clock is divide by 4 and generated by passi ng pulses 0..4..8.. et c, then the neagtive phase clock will be generated by passing pulses 2..6..10.. ?t dh for the memory will be t ebu /2+t dh1 -(n 1) /2*t jit 2) ) ?t ds for the memory will be t ebu /4-t ds1 -(n/2*t jit ) ? if the ebu internal clock is a buffered version of the system clock input then the negative phase clock will be an invert ed version of the system clock ?t dh for the memory will be t ck /4+t dh1 -t jit2 3) ?t ds for the memory will be t ck /4-t ds1 -t jit2 ? if the duty cycle correction function of t he dll is enabled, then the negative phase clock will be the main clock delayed by 0.5*t ck ?t dh for the memory will be t dcc +t dh1 ?t ds for the memory will be t dcc -t ds1 1:4 internal to external clock ratio if the external bus clock is running at one quarter the internal clock frequency, then ebu internal clock clock is used to generate intermediate clock edges at the intervals necessary to correctly position the transitions on dq and dm the negative phase clock is generated either by: ?t dh for the memory will be t ebu +t dh1 -t jit ?t ds for the memory will be t ebu -t ds1 -t jit timing of ddr read data ddr read data can be captured in two modes. the first mode uses the dll to shift the dqs signals internally to provide setu p and hold margins between the dqs and dq lines. the dqs signals are then used as a clock to latch the data into internal registers. the second mode is suitable only for lower frequencies and uses the ddrclko signal internally as a clock to latch both the dq and dqs signals. the state of the latched dqs 1) where n is the divide ratio between the system clock input and the ebu internal clock 2) t jit is the pk-pk clock jitter of the system clock source 3) t jit2 is the rising to falling edge jitter of the system clock source
TC1798 electrical parametersac parameters data sheet 181 v 1.1, 2014-05 signal is used to determine whether dq is va lid at any given clock edge. the restriction is that the ddrclko signal must propagat e through the TC1798 output pad in both directions in time for the dq and dqs signals to be latched before the next rising edge of ddrclko at the clock generating flip-flop inside the ebu, i.e. (pad output delay)+(pad input delay)+(latch ck->q valid) = t time < t ck in addition the clock to output valid delay of the attached memory device must be less than 0.5 * t ck dll controlled read the ebu interface is characterised with the dll disabled. the relative positioning of the dq and dqs edges are then adjusted to determine the setup and hold times. the parameters in the following table are therefore specified with the dll inactive a standard ddr device will output the dq and dqs signals with edges that are nominally aligned and the dll will delay the dqs inputs internally to re-establish the setup and hold margins. figure 32 dll co ntrolled read once the dll is enabled, to satisfy the se tup time, the dq outp ut from the memory device must be valid less than t dllr -t qs ns after the dqs edge. to satisfy the hold time, the dq output from the memory device must remain valid until the time (t ck /2)-t jitn -t dllr -t dh before the next dqs edge. ddrclko controlled read a standard ddr device will output the dq and dqs signals with edges that are nominally aligned. in this mode, the data wil l be latched on both edges of the feedback clock. this clock is generated from ddrclko . ddrclko dqs[3:0] don't care data valid transitioning data t0 t1 t2 dq[31:0] t qs ddrclko t qh t qs t qh
TC1798 electrical parametersflash memory parameters data sheet 182 v 1.1, 2014-05 figure 33 ddrclko controlled read in order for the read data to be captured successfully, the maximum clock to dqs & dq valid limit for the attached memory device must be less than half an external bus clock period by the setup margin, t dqcks and the hold time for the dqs and data after the clock edge must be greater than t dqckh . timing of sdram read data for sdram read accesses, ddrclko (s dclko) must be connected to ddrclko (sdclki) to establish a path for the feedback clock. then tdqcks and tdqckh can be used to calculate timing margins in the same ways as for a ddr read except that only the rising edge of sdclki is used for capturing data. in order for the read data to be captured successfully, the maximum clock to dq valid limit for the attached memory device must be less than an external bus clock period by the setup margin, t dqcks and the hold time for the data after the clock edge must be greater than t dqckh . 5.4 flash memory parameters the data retention time of the TC1798?s fl ash memory depends on the number of times the flash memory has been erased and programmed. table 46 flash32 parameters parameter symbol values unit note / test condition min. typ. max. data flash erase time per sector t erd cc ?? 4.2 1) s program flash erase time per 256 kbyte sector t erp cc ?? 5s ddrclko dqs[3:0] don't care data valid transitioning data t0 t1 t2 dq[31:0] ddrclko t dqcks t dqcks t dqckh t dqckh
TC1798 electrical parametersflash memory parameters data sheet 183 v 1.1, 2014-05 program time data flash per page 2) t prd cc ?? 5.3 ms without reprogramming ?? 15.9 ms with two reprogramming cycles program time program flash per page 3) t prp cc ?? 5.3 ms without reprogramming ?? 10.6 ms with one reprogramming cycle data flash endurance n e cc 60000 4) ?? cycle s min. data retention time 5 years erase suspend delay t fl_ersusp cc ?? 15 ms wait time after margin change t fl_margin del cc 10 ?? s aborted logical sector erase soft-programming recovery t fl_spre c cc ?? 400 ms program flash retention time, physical sector 5)6) t ret cc 20 ?? year s max. 1000 erase/program cycles program flash retention time, logical sector 5)6) t retl cc 20 ?? year s max. 100 erase/program cycles ucb retention time 5)6) t rtu cc 20 ?? year s max. 4 erase/program cycles per ucb wake-up time t wu cc ?? 270 s dflash wait state configuration ws df cc 50 ns x f fsi ?? pflash wait state configuration ws pf cc 26 ns x f fsi ?? table 46 flash32 parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
TC1798 electrical parametersflash memory parameters data sheet 184 v 1.1, 2014-05 1) in case of wordline oriented defects (see robust eeprom emulation in the user's manual) this erase time can increase by up to 100%. 2) in case the program verify featur e detects weak bits, these bits will be programmed up to twice more. each reprogramming takes additional 5 ms. 3) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5 ms. 4) only valid when a robust eeprom emulation algorith m is used. for more details see the users manual. 5) storage and inactive time included. 6) at average weighted junction temperature t j = 100c, or the retention time at average weighted temperature of t j = 110c is minimum 10 years, or the retention time at average weighted temperature of t j = 150c is minimum 0.7 years.
TC1798 electrical parameterspackage and reliability data sheet 185 v 1.1, 2014-05 5.5 package and reliability 5.5.1 package parameters table 47 thermal characteristics of the package device package r jct 1) 1) the top and bottom thermal resistances between the case and the ambient ( r tcat , r tcab ) are to be combined with the thermal resistances between the junction and the case given above ( r tjct , r tjcb ), in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tcat , r tcab ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction a nd the ambient. this total junction ambient resistance r tja can be obtained from the upper fo ur partial thermal resistances. thermal resistances as measured by the ?cold plate method? (mil spec-883 method 1012.1). r jcb 1) r ja unit note TC1798 pg-lfbga- 516 3,5 6,1 14,7 k/w
TC1798 electrical parameterspackage and reliability data sheet 186 v 1.1, 2014-05 5.5.2 package outline figure 34 package outlines pg-lfbga- 516 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://ww w.infineon.com/products. 5.5.3 quality declarations table 48 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime 1) t op ? ? 24000 hours ? 2) esd susceptibility according to human body model (hbm) v hbm ? ? 2000 v conforming to jesd22-a114-b esd susceptibility of the lvds pins v hbm1 ?? 500v ?
TC1798 electrical parameterspackage and reliability data sheet 187 v 1.1, 2014-05 esd susceptibility according to charged device model (cdm) v cdm ? ? 500 v conforming to jesd22-c101-c moisture sensitivity level msl ? ? 3 ? conforming to jedec j-std-020c for 240c 1) this lifetime refers only to the time when the device is powered on. 2) for worst-case temperature profile equivalent to: 1200 hours at t j = 125...150 o c 3600 hours at t j = 110...125 o c 7200 hours at t j = 100...110 o c 11000 hours at t j = 25...110 o c 1000 hours at t j = -40...25 o c table 48 quality parameters parameter symbol values unit note / test condition min. typ. max.
TC1798 history data sheet 1 v 1.1, 2014-05 6history the following changes where done between ve rsion 0.6 and 0.62 of this document: ? change wdith for port 2 in figure 2 ? change numbers of v ddfl3 and v ss in figure 2 ? update figure 3 according to pinning changes ? remove typo in ctrl. line from i/o0 to i/o ? change for port 2.8 the symbol from ctrapb (ccu60) to ccpos0a (ccu62) ? change for port 2.8 the symbol from t13hre (ccu61) to t12hrb (ccu63) ? add for port 2.8 the symbol from t3inb (gpt120) ? add for port 2.8 the symbol from t3ina (gpt121) ? change for port 2.10 the symbol from cc60inc (ccu61) to ctrapb (ccu63) ? change for port 2.12 the symbol from ctrapb (ccu61) to ccpos0a (ccu63) ? change for port 2.12 the symbol from t13hre (ccu60) to t12hrb (ccu62) ? add for port 2.12 the symbol from t2inb (gpt120) ? add for port 2.12 the symbol from t2ina (gpt121) ? add for port 3.0 the symbol ctrapb (ccu61) ? change for port 3.0 for symbol cc60inc from ccu62 to ccu61 ? move pin p3.1 from b20 to b22 ? move pin p3.2 from j19 to a22 ? move pin p3.3 from a20 to b21 ? move pin p3.4 from g19 to k18 ? move pin p3.5 from b19 to a21 ? move pin p3.6 from k18 to b19 ? move pin p3.7 from a19 to a20 ? move pin p3.8 from j18 to b19 ? move pin p3.9 from b18 to a19 ? move pin p3.10 from g18 to j18 ? move pin p3.11 from a18 to b18 ? move pin p3.12 from f18 to k17 ? move pin p3.13 from b13 to a18 ? move pin p3.14 from k17 to b13 ? removed for port 3.2 the symbol ctrapb (ccu62) ? add for port 3.4 the symbol ctrapa (ccu63) ? change for port 3.4 the symbol from cc61inc (ccu62) to ctrapb (ccu60) ? ? removed for port 3.6 the symbol ctrapb (ccu63) ? change for port 3.8 the symbol from t12hrb (ccu63) to t13hre (ccu61) ? removed for port 3.8 the symbol ccpos0a (ccu62) ? removed for port 3.8 the symbol t3inb (gpt120) ? removed for port 3.8 the symbol t3ina (gpt121) ? change for port 3.14 the symbol from t12hrb (ccu62) to t13hre (ccu60) ? removed for port 3.14 the symbol ccpos0a (ccu63)
TC1798 history data sheet 2 v 1.1, 2014-05 ? removed for port 3.14 the symbol t2inb (gpt120) ? removed for port 3.14 the symbol t2ina (gpt121) ? change function description for port 4.1 alternate output 3 mtsr2 from slave to master mode ? add footnote to port 4. 1 alternate output 3 mtsr2 ? change function description for port 4.1 alternate output 3 mtsr2 from slave to master transmit ? move pin p5.12 from b22 to j19 ? move pin p5.12 from b23 to g19 ? move pin p5.12 from a22 to g18 ? move pin p5.12 from a23 to f18 ? add footnote to port 6. 4 alternate output 1 mtsr1 ? change for port 7.0 the symbol from ademux0 to ademux2 ? change function description for port 7.1 alternate output 2 mtsr3 from slave to master mode ? add footnote to port 7. 1 alternate output 2 mtsr3 ? change for port 8.3 the symbol from out43 (gpta1) to cc62 (ccu60) ? add for port 8.5 the symbol ctrapb (ccu62) ? change for port 9.13 the symbol from ectt2 to ectt1 ? change for port 9.14 the symbol from ectt1 to ectt2 ? add for port 9.14 the symbol req15 ? add footnote to port 10.1 alternate output 1 mtsr0 ? change for port 15 the type from s to d / s ? change function description for port 18.1 alternate input mtsr 2b from master to slave mode ? change function description for port 18. 1 alternate output 1 mtsr2 from slave to master mode ? add footnote to port 18.1 alternate output 1 mtsr2 ? move pin v ddp from ad15 to ad16 ? add clarification that table 9 defines the conditions for all other parameters ? add conditions for mli, msc, ssc, parameters ? add parameters dtxdly an d drxdly to eray parameters ? correct footnotes for eray parameters ? split flash parameters tprd and tprp in two conditions ? add conditions to lvds pad parameters ? remove pin reliability in overload section ? add parameters iin and sum iin to absolute ratings ? add parameter hysx to psc_xtal ? added rdson values for all driver settings (weak, medium, and strong) ? removed footnote 2 of table 10 ? change load for timing of ssc, msc, and mli from c l =25pf to c l = 50 pf (typical) ? add to parameters t rf and t ff condition c l =50pf ? add new footnote 7) to adc parameter table
TC1798 history data sheet 3 v 1.1, 2014-05 ? add min and max value for q conv and adapt typ value ? add load conditions for t ff1 and t rf1 ? add conditions to pll parameter t l ? change dap parameter t 19 from sr to cc classification ? remove footnote 2 for the fadc ? adapt ids for ab step ? move pin an49 from w2 to w1 ? move pin an48 from w1 to w2 ? removed footnote 2 in table 9 ? change max value for adc parameter t s from 255 to 257 ? ? change p1.7 input cc60inb to cc61inb ? remove o2 out105 for gpta1 of p14.9 ? add o2 t3out for gpt121 of p14.9 ? changed the name for o3 from evto2 to evto1 for p0.5 ? changed the name for o3 from evto3 to evto2 for p0.6 ? changed the name for o3 from evto4 to evto3 for p0.7 ? changed the name for o1 and o2 from out70 to out71 for p1.15 ? add input function slsi2 for ssc2 to p4.9 the following changes where done between version 0.62 and 0.63 of this document: ? change p1.7 input cc60inb to cc61inb ? remove o2 out105 for gpta1 of p14.9 ? add o2 t3out for gpt121 of p14.9 ? changed the name for o3 from evto2 to evto1 for p0.5 ? changed the name for o3 from evto3 to evto2 for p0.6 ? changed the name for o3 from evto4 to evto3 for p0.7 ? changed the name for o1 and o2 from out70 to out71 for p1.15 ? add input function slsi2 for ssc2 to p4.9 ? add input function cc60inc forccu61 for p2.10 ? change back for port 3.0 for symbol cc60inc from ccu61 to ccu62 ? change input function t13hre from ccu60 to ccu63 ? change for port 6.15 the symbol from cc61(ccu60) to cc60(ccu61) ? change for port 8.2 the symbol from cc61(ccu60) to cout63(ccu61) ? change for port 14.10 the symbol from t3out(gpt120) to t6out(gpt121) ? add to all ssc signal the assosiated ssc module where is was missing in the pinning ? add section pin reliability in overload ? incease values for absolute maximium parameters i in and sum i in ? correct p14.8 o2 as this was incorrected label as o1 the following changes where done between version 0.63 and 0.7 of this document: ? change value r jct from 2.6 to 3.5 k/w ? change value r jcb from 4.3 to 6.1 k/w ? change value r ja from 13.6 to 14.7 k/w
TC1798 history data sheet 4 v 1.1, 2014-05 ? add parameter t por_app ? replace in operating conditions parameter note ma = modulation amplitude by footnote 1) ? remove the redundant test condition i oh for rdson nmos ? remove the redundant test condition i ol for rdson pmos ? add parameter v ilsd to class s pads ? remove footnote 2 from fadc ? remove capacitance conditions for lv ds pad parameters as loads are defined by interface (msc) timings the following changes where done between ve rsion 0.7 and 1.0 of this document: ? add product options sak-TC1798s-512f300ep and sak-TC1798n-512f300ep ? remove product options sak-TC1798f-512f240ep and sak-TC1798f- 512f240el ? update block diagrams to cover new options ? add note to TC1798 logic symbol figure and pin list for e-ray pins availability ? add identification registers for new options ? adapt absolute maximum rating ? clarify pad supply levels in pin reliability in overload section ? correct errors for analog inputs in tables 10 and 11 ? add note at the end of pin reliability in overload section ? clarify wording for valid operating conditions ? correct section extended range oper ating conditions for the 3.3 v area ? increase limit in extended range operating conditions from 1 hour to 1000 hours ? add negative limit for class s pad leakage ? removed rdson parameters for class f p ads weak driver as only medium is available and update values ? change description of parameter t cal for the adc ? update footnote 10 for the adc ? update definition of inl and tue for adc3 ? split fadc dnl parameter into two conditions and change value for gain 4 and 8 ? update all current values of table 28 (power supply parameters) ? add footnote 5 to i ddp ? improve parameters i ddfl3 ? add footnote for d-flash currents in power section ? add section 5.2.6.1. ? rework first sentence for chapter 5.3 ? increase max values for parameter t b ? reduce min value for t l for both plls ? split f vco for the system pll into two conditions ? change formula 10 ? add for mli and ssc timing parameter: valid strong driver medium edge only ? change mli parameter t 17 min value
TC1798 history data sheet 5 v 1.1, 2014-05 ? update parameter description for ssc parameters t 52 , t 53 , t 56 , t 57 , t 58 , and t 59 ? change ssc parameters from cc to sr symbol for t 56 , t 57 , t 58 and t 59 ? add note to eray parameters for availability ? add parameters t 15 , t 16 , t 17 , t 18 , and t 19 to the ebu ? adapt ebu parameters for ddr timming ? add footnote to flash parameter t erd ? change for parameter n e note from max. data retention to min. ? rework the 3.3 v current part of the powe r supply parameters for better description and usage ? parameters i ddp_fp , i ddfl3e and i ddfl3r are removed and replaced in the following way ? i ddp_fp is replaced by i ddp with the condition including flash programming current ? i ddfl3e is replaced by i ddp with the condition including flash erase verify current ? i ddfl3r is replaced by i ddp with the condition including flash read current ? parameter i ddfl3r was renamed to i ddfl3 the rework of the 3.3 v current part of the power supply parameters was done for simplification and clarification. former given values could still be used if liked, the new definition results in the same resulting values or slightly better values. the flash module is supplied via i ddfl3 and i ddp . for the different flash operating modes in worst case different allocations for the two domains resulting. the application typical case ?flash read? has max i ddp of 25 ma and max i ddfl3 of 98 ma resulting is a sum of 123 ma. the case ?flash pr ogramming? has max i ddp of 55 ma and max i ddfl3 of 29 ma resulting is a sum of 84 ma. the case ?flash erase verify? has max i ddp of 40 ma and max i ddfl3 of 98 ma resulting is a sum of 138 ma. so for the old parameter i ddp with 35 ma, the new version reads as i ddp = 25+ i ddp_porst = 32 ma for the same applic ation relevant case. the following changes where done between ve rsion 1.0 and 1.1 of this document: ? change v ils from 2.1v to 1.9v in table 23 ? change t 48 from 100ns to 200ns in table 42 ? change t 49 from 100ns to 200ns in table 42 ? extend k ovan conditon from i ov 0ma; i ov -1 ma to i ov 0ma; i ov -2 ma ? change t 8 from -4ns to -2ns in table 43 ? change t 18 from -4ns to -2ns in table 43 ? change t 37 parameter description from ?data output delay to wr rising edge, deviation from the ideal programmed value? to ?data output delay to wr falling edge, deviation from the ideal programmed value? in table 44 ? add r dsonx information for class b pads to table 18 ? add exact definition ?edge= sharp ; pin out driver= strong? for the pad conviguration of the rise and fall times in table 18
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